[PATCH v2 0/5] RISC-V big endian support

[Maciej W. Rozycki]

On Sun, 14 Mar 2021, Marcus Comstedt wrote:

> How would you like to proceed?  I don't feel confident that I will
> find a definitive solution to this issue anytime soon, but it feels
> like such a weird special case (who passes 64-bit floats in 32-bit
> integer registers to their asm?) that it might be ok to just ignore
> it.  If you agree I'll just repost the patchset with the final fix
> added (solves all remaining 32-bit testcases save for this one)...

 Soft-float use case?  Also VAX does even for hard float as it does not 
have separate FPRs, but then it is little-endian exclusively too.

 Overall I think this is analogous to `long long' with 32-bit targets, 
though individual psABIs may specify different conventions as to the order 
of the two parts of the FP datum between the registers in such a pair.

  Maciej