[PATCH] i386: Add V2SFmode vec_addsub pattern [PR95046]

Uros Bizjak ubizjak@gmail.com
Tue Jun 29 17:19:33 GMT 2021


gcc/

2021-06-21  Uroš Bizjak  <ubizjak@gmail.com>

    PR target/95046
    * config/i386/mmx.md (vec_addsubv2sf3): New insn pattern.

gcc/testsuite/

2021-06-21  Uroš Bizjak  <ubizjak@gmail.com>

    PR target/95046
    * gcc.target/i386/pr95046-9.c: New test.

Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.

Pushed to master.

Uros.
-------------- next part --------------
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index e887f03474d..5f10572718d 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -788,6 +788,24 @@ (define_insn "*mmx_haddsubv2sf3"
    (set_attr "prefix_extra" "1")
    (set_attr "mode" "V2SF")])
 
+(define_insn "vec_addsubv2sf3"
+  [(set (match_operand:V2SF 0 "register_operand" "=x,x")
+	(vec_merge:V2SF
+	  (minus:V2SF
+	    (match_operand:V2SF 1 "register_operand" "0,x")
+	    (match_operand:V2SF 2 "register_operand" "x,x"))
+	  (plus:V2SF (match_dup 1) (match_dup 2))
+	  (const_int 1)))]
+  "TARGET_SSE3 && TARGET_MMX_WITH_SSE"
+  "@
+   addsubps\t{%2, %0|%0, %2}
+   vaddsubps\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sseadd")
+   (set_attr "prefix" "orig,vex")
+   (set_attr "prefix_rep" "1,*")
+   (set_attr "mode" "V4SF")])
+
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;
 ;; Parallel single-precision floating point comparisons
diff --git a/gcc/testsuite/gcc.target/i386/pr95046-9.c b/gcc/testsuite/gcc.target/i386/pr95046-9.c
new file mode 100644
index 00000000000..54e948ccfb0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr95046-9.c
@@ -0,0 +1,14 @@
+/* PR target/95046 */
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O3 -msse3" } */
+
+float r[2], a[2], b[2];
+
+void
+test (void)
+{
+  r[0] = a[0] - b[0];
+  r[1] = a[1] + b[1];
+}
+
+/* { dg-final { scan-assembler "\tv?addsubps" } } */


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