[PATCH 0/2] RISC-V: Add ldr/str instruction for T-HEAD.

Jojo R rjiejie@linux.alibaba.com
Tue Jun 29 08:11:05 GMT 2021

T-HEAD extends some customized ISAs for Cores.
The patches support ldr/str insns, it likes arm's LDR insn, the
memory model is a base register indexed by (optionally scaled) register.

More information about the Gcc-patches mailing list