[PATCH V2] aarch64: Model zero-high-half semantics of XTN instruction in RTL

Jonathan Wright Jonathan.Wright@arm.com
Wed Jun 16 09:04:57 GMT 2021


Hi,

Version 2 of this patch adds tests to verify the benefit of this change.

Ok for master?

Thanks,
Jonathan

---

gcc/ChangeLog:

2021-06-11  Jonathan Wright  <jonathan.wright@arm.com>

	* config/aarch64/aarch64-simd.md (aarch64_xtn<mode>_insn_le):
	Define - modeling zero-high-half semantics.
	(aarch64_xtn<mode>): Change to an expander that emits the
	appropriate instruction depending on endianness.
	(aarch64_xtn<mode>_insn_be): Define - modeling zero-high-half
	semantics.
	(aarch64_xtn2<mode>_le): Rename to...
	(aarch64_xtn2<mode>_insn_le): This.
	(aarch64_xtn2<mode>_be): Rename to...
	(aarch64_xtn2<mode>_insn_be): This.
	(vec_pack_trunc_<mode>): Emit truncation instruction instead
	of aarch64_xtn.
	* config/aarch64/iterators.md (Vnarrowd): Add Vnarrowd mode
	attribute iterator.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/narrow_zero_high_half.c: Add new tests.


From: Gcc-patches <gcc-patches-bounces+jonathan.wright=arm.com@gcc.gnu.org> on behalf of Jonathan Wright via Gcc-patches <gcc-patches@gcc.gnu.org>
Sent: 15 June 2021 10:45
To: gcc-patches@gcc.gnu.org <gcc-patches@gcc.gnu.org>
Subject: [PATCH] aarch64: Model zero-high-half semantics of XTN instruction in RTL 
 
Hi,

Modeling the zero-high-half semantics of the XTN narrowing
instruction in RTL indicates to the compiler that this is a totally
destructive operation. This enables more RTL simplifications and also
prevents some register allocation issues.

Regression tested and bootstrapped on aarch64-none-linux-gnu - no
issues.

Ok for master?

Thanks,
Jonathan

---

gcc/ChangeLog:

2021-06-11  Jonathan Wright  <jonathan.wright@arm.com>

        * config/aarch64/aarch64-simd.md (aarch64_xtn<mode>_insn_le):
        Define - modeling zero-high-half semantics.
        (aarch64_xtn<mode>): Change to an expander that emits the
        appropriate instruction depending on endianness.
        (aarch64_xtn<mode>_insn_be): Define - modeling zero-high-half
        semantics.
        (aarch64_xtn2<mode>_le): Rename to...
        (aarch64_xtn2<mode>_insn_le): This.
        (aarch64_xtn2<mode>_be): Rename to...
        (aarch64_xtn2<mode>_insn_be): This.
        (vec_pack_trunc_<mode>): Emit truncation instruction instead
        of aarch64_xtn.
        * config/aarch64/iterators.md (Vnarrowd): Add Vnarrowd mode
        attribute iterator.
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