[PATCH, rs6000] Update Power10 scheduling description for fused instruction types
Pat Haugen
pthaugen@linux.ibm.com
Mon Jun 7 20:41:29 GMT 2021
Update Power10 scheduling description for new fused instruction types.
Bootstrap/regtest on powerpc64le(Power10) with no new regressions. Ok for
trunk?
-Pat
2021-06-07 Pat Haugen <pthaugen@linux.ibm.com>
gcc/ChangeLog:
* config/rs6000/power10.md (power10-fused-load, power10-fused-store,
power10-fused_alu, power10-fused-vec, power10-fused-branch): New.
diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md
index 665f0f22c62..0186ae95896 100644
--- a/gcc/config/rs6000/power10.md
+++ b/gcc/config/rs6000/power10.md
@@ -100,6 +100,11 @@ (define_insn_reservation "power10-load" 4
(eq_attr "cpu" "power10"))
"DU_any_power10,LU_power10")
+(define_insn_reservation "power10-fused-load" 4
+ (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load")
+ (eq_attr "cpu" "power10"))
+ "DU_even_power10,LU_power10")
+
(define_insn_reservation "power10-prefixed-load" 4
(and (eq_attr "type" "load")
(eq_attr "update" "no")
@@ -176,6 +181,11 @@ (define_insn_reservation "power10-store" 0
(eq_attr "cpu" "power10"))
"DU_any_power10,STU_power10")
+(define_insn_reservation "power10-fused-store" 0
+ (and (eq_attr "type" "fused_store_store")
+ (eq_attr "cpu" "power10"))
+ "DU_even_power10,STU_power10")
+
(define_insn_reservation "power10-prefixed-store" 0
(and (eq_attr "type" "store,fpstore,vecstore")
(eq_attr "prefixed" "yes")
@@ -244,6 +254,11 @@ (define_insn_reservation "power10-alu" 2
(define_bypass 4 "power10-alu"
"power10-crlogical,power10-mfcr,power10-mfcrf")
+(define_insn_reservation "power10-fused_alu" 2
+ (and (eq_attr "type" "fused_arith_logical,fused_cmp_isel,fused_carry")
+ (eq_attr "cpu" "power10"))
+ "DU_even_power10,EXU_power10")
+
; paddi
(define_insn_reservation "power10-paddi" 2
(and (eq_attr "type" "add")
@@ -403,6 +418,11 @@ (define_insn_reservation "power10-vec-2cyc" 2
(eq_attr "cpu" "power10"))
"DU_any_power10,EXU_power10")
+(define_insn_reservation "power10-fused-vec" 2
+ (and (eq_attr "type" "fused_vector")
+ (eq_attr "cpu" "power10"))
+ "DU_even_power10,EXU_power10")
+
(define_insn_reservation "power10-veccmp" 3
(and (eq_attr "type" "veccmp")
(eq_attr "cpu" "power10"))
@@ -490,6 +510,11 @@ (define_insn_reservation "power10-branch" 2
(eq_attr "cpu" "power10"))
"DU_any_power10,STU_power10")
+(define_insn_reservation "power10-fused-branch" 3
+ (and (eq_attr "type" "fused_mtbc")
+ (eq_attr "cpu" "power10"))
+ "DU_even_power10,STU_power10")
+
; Crypto
(define_insn_reservation "power10-crypto" 4
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