[RFC/PATCH 00/11] Fix up some unexpected empty split conditions
Kewen.Lin
linkw@linux.ibm.com
Fri Jun 4 02:57:51 GMT 2021
Hi Segher,
on 2021/6/3 下午5:18, Segher Boessenkool wrote:
> On Thu, Jun 03, 2021 at 03:00:44AM -0500, Segher Boessenkool wrote:
>> On Thu, Jun 03, 2021 at 01:22:38PM +0800, Kewen.Lin wrote:
>> The whole point of requiring the split condition to start with && is so
>> it will become harder to mess things up (it will make the gen* code a
>> tiny little bit simpler as well). And there is no transition period or
>> anything like that needed either. Just the bunch that will break will
>> need fixing. So let's find out how many of those there are :-)
>>
To find out those need fixing seems to be the critical part. It's
not hard to add one explicit "&&" to those that don't have it now, but
even with further bootstrapped and regression tested I'm still not
confident the adjustments are safe enough, since the testing coverage
could be limited. It may need more efforts to revisit, or/and test
with more coverages, and port maintainers' reviews.
In order to find one example which needs more fixing, for rs6000/i386/
aarch64, I fixed all define_insn_and_splits whose insn cond isn't empty
(from gensupport's view since the iterator can add more on) while split
cond don't start with "&&" , also skipped those whose insn conds are
the same as their split conds. Unfortunately (or fortunately :-\) all
were bootstrapped and regress-tested.
The related diffs are attached, which is based on r12-0.
>>>> How many such cases *are* there? There are no users exposed to this,
>>>> and when the split condition is required to start with "&&" (instead of
>>>> getting that implied) it is not a silent change ever, either.
>>>
>>> If I read the proposal right, the explicit "&&" is only required when going
>>> to find all potential problematic places for final implied "&&" change.
>>> But one explicit "&&" does offer good readability.
>>
>> My proposal is to always require && (or maybe identical insn and split
>> conditions should be allowed as well, if people still use that -- that
>> is how we wrote "&& 1" before that existed).
>
> I prototyped this. There are very many errors. Iterators often modify
> the insn condition (for one iteration of it), but that does not work if
> the split condition does not start with "&&"!
>
> See attached prototype.
>
>
Thanks for the prototype!
BR,
Kewen
> Segher
>
> = = =
>
> diff --git a/gcc/gensupport.c b/gcc/gensupport.c
> index 2cb760ffb90f..05d46fd3775c 100644
> --- a/gcc/gensupport.c
> +++ b/gcc/gensupport.c
> @@ -590,7 +590,6 @@ process_rtx (rtx desc, file_location loc)
> case DEFINE_INSN_AND_SPLIT:
> case DEFINE_INSN_AND_REWRITE:
> {
> - const char *split_cond;
> rtx split;
> rtvec attr;
> int i;
> @@ -611,15 +610,20 @@ process_rtx (rtx desc, file_location loc)
>
> /* If the split condition starts with "&&", append it to the
> insn condition to create the new split condition. */
> - split_cond = XSTR (desc, 4);
> - if (split_cond[0] == '&' && split_cond[1] == '&')
> + const char *insn_cond = XSTR (desc, 2);
> + const char *split_cond = XSTR (desc, 4);
> + if (!strncmp (split_cond, "&&", 2))
> {
> rtx_reader_ptr->copy_md_ptr_loc (split_cond + 2, split_cond);
> - split_cond = rtx_reader_ptr->join_c_conditions (XSTR (desc, 2),
> + split_cond = rtx_reader_ptr->join_c_conditions (insn_cond,
> split_cond + 2);
> + } else if (insn_cond[0]) {
> + if (GET_CODE (desc) == DEFINE_INSN_AND_REWRITE)
> + error_at (loc, "the rewrite condition must start with `&&'");
> + else
> + error_at (loc, "the split condition must start with `&&' [%s]", insn_cond);
> }
> - else if (GET_CODE (desc) == DEFINE_INSN_AND_REWRITE)
> - error_at (loc, "the rewrite condition must start with `&&'");
> +
> XSTR (split, 1) = split_cond;
> if (GET_CODE (desc) == DEFINE_INSN_AND_REWRITE)
> XVEC (split, 2) = gen_rewrite_sequence (XVEC (desc, 1));
>
-------------- next part --------------
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index abfd845..86869d9 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -1283,7 +1283,7 @@ (define_insn_and_split "*movsi_aarch64"
fmov\\t%w0, %s1
fmov\\t%s0, %s1
* return aarch64_output_scalar_simd_mov_immediate (operands[1], SImode);"
- "CONST_INT_P (operands[1]) && !aarch64_move_imm (INTVAL (operands[1]), SImode)
+ "&& CONST_INT_P (operands[1]) && !aarch64_move_imm (INTVAL (operands[1]), SImode)
&& REG_P (operands[0]) && GP_REGNUM_P (REGNO (operands[0]))"
[(const_int 0)]
"{
@@ -1319,7 +1319,7 @@ (define_insn_and_split "*movdi_aarch64"
fmov\\t%x0, %d1
fmov\\t%d0, %d1
* return aarch64_output_scalar_simd_mov_immediate (operands[1], DImode);"
- "(CONST_INT_P (operands[1]) && !aarch64_move_imm (INTVAL (operands[1]), DImode))
+ "&& (CONST_INT_P (operands[1]) && !aarch64_move_imm (INTVAL (operands[1]), DImode))
&& REG_P (operands[0]) && GP_REGNUM_P (REGNO (operands[0]))"
[(const_int 0)]
"{
-------------- next part --------------
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 9ff35d9..8d72f34 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -5249,7 +5249,7 @@ (define_insn_and_split "*add<dwi>3_doubleword"
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (PLUS, <DWI>mode, operands)"
"#"
- "reload_completed"
+ "&& reload_completed"
[(parallel [(set (reg:CCC FLAGS_REG)
(compare:CCC
(plus:DWIH (match_dup 1) (match_dup 2))
@@ -6050,7 +6050,7 @@ (define_insn_and_split "*addv<dwi>4_doubleword"
(plus:<DWI> (match_dup 1) (match_dup 2)))]
"ix86_binary_operator_ok (PLUS, <DWI>mode, operands)"
"#"
- "reload_completed"
+ "&& reload_completed"
[(parallel [(set (reg:CCC FLAGS_REG)
(compare:CCC
(plus:DWIH (match_dup 1) (match_dup 2))
@@ -6097,7 +6097,7 @@ (define_insn_and_split "*addv<dwi>4_doubleword_1"
&& CONST_SCALAR_INT_P (operands[2])
&& rtx_equal_p (operands[2], operands[3])"
"#"
- "reload_completed"
+ "&& reload_completed"
[(parallel [(set (reg:CCC FLAGS_REG)
(compare:CCC
(plus:DWIH (match_dup 1) (match_dup 2))
@@ -6391,7 +6391,7 @@ (define_insn_and_split "*sub<dwi>3_doubleword"
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (MINUS, <MODE>mode, operands)"
"#"
- "reload_completed"
+ "&& reload_completed"
[(parallel [(set (reg:CC FLAGS_REG)
(compare:CC (match_dup 1) (match_dup 2)))
(set (match_dup 0)
@@ -6559,7 +6559,7 @@ (define_insn_and_split "*subv<dwi>4_doubleword"
(minus:<DWI> (match_dup 1) (match_dup 2)))]
"ix86_binary_operator_ok (MINUS, <MODE>mode, operands)"
"#"
- "reload_completed"
+ "&& reload_completed"
[(parallel [(set (reg:CC FLAGS_REG)
(compare:CC (match_dup 1) (match_dup 2)))
(set (match_dup 0)
@@ -6604,7 +6604,7 @@ (define_insn_and_split "*subv<dwi>4_doubleword_1"
&& CONST_SCALAR_INT_P (operands[2])
&& rtx_equal_p (operands[2], operands[3])"
"#"
- "reload_completed"
+ "&& reload_completed"
[(parallel [(set (reg:CC FLAGS_REG)
(compare:CC (match_dup 1) (match_dup 2)))
(set (match_dup 0)
@@ -7204,7 +7204,7 @@ (define_insn_and_split "*add<dwi>3_doubleword_cc_overflow_1"
(plus:<DWI> (match_dup 1) (match_dup 2)))]
"ix86_binary_operator_ok (PLUS, <DWI>mode, operands)"
"#"
- "reload_completed"
+ "&& reload_completed"
[(parallel [(set (reg:CCC FLAGS_REG)
(compare:CCC
(plus:DWIH (match_dup 1) (match_dup 2))
@@ -8161,7 +8161,7 @@ (define_insn_and_split "divmod<mode>4_1"
(clobber (reg:CC FLAGS_REG))]
""
"#"
- "reload_completed"
+ "&& reload_completed"
[(parallel [(set (match_dup 1)
(ashiftrt:SWI48 (match_dup 4) (match_dup 5)))
(clobber (reg:CC FLAGS_REG))])
@@ -8196,7 +8196,7 @@ (define_insn_and_split "udivmod<mode>4_1"
(clobber (reg:CC FLAGS_REG))]
""
"#"
- "reload_completed"
+ "&& reload_completed"
[(set (match_dup 1) (const_int 0))
(parallel [(set (match_dup 0)
(udiv:SWI48 (match_dup 2) (match_dup 3)))
@@ -8336,7 +8336,7 @@ (define_insn_and_split "*divmod<mode>4"
(clobber (reg:CC FLAGS_REG))]
""
"#"
- "reload_completed"
+ "&& reload_completed"
[(parallel [(set (match_dup 1)
(ashiftrt:SWIM248 (match_dup 4) (match_dup 5)))
(clobber (reg:CC FLAGS_REG))])
@@ -8371,7 +8371,7 @@ (define_insn_and_split "*udivmod<mode>4"
(clobber (reg:CC FLAGS_REG))]
""
"#"
- "reload_completed"
+ "&& reload_completed"
[(set (match_dup 1) (const_int 0))
(parallel [(set (match_dup 0)
(udiv:SWIM248 (match_dup 2) (match_dup 3)))
@@ -10069,7 +10069,7 @@ (define_insn_and_split "*neg<dwi>2_doubleword"
(clobber (reg:CC FLAGS_REG))]
"ix86_unary_operator_ok (NEG, <DWI>mode, operands)"
"#"
- "reload_completed"
+ "&& reload_completed"
[(parallel
[(set (reg:CCC FLAGS_REG)
(ne:CCC (match_dup 1) (const_int 0)))
@@ -11545,7 +11545,7 @@ (define_insn_and_split "*<insn><mode>3_doubleword"
(clobber (reg:CC FLAGS_REG))]
""
"#"
- "epilogue_completed"
+ "&& epilogue_completed"
[(const_int 0)]
"ix86_split_<insn> (operands, NULL_RTX, <MODE>mode); DONE;"
[(set_attr "type" "multi")])
@@ -12045,7 +12045,7 @@ (define_insn_and_split "ix86_rotl<dwi>3_doubleword"
(clobber (match_scratch:DWIH 3 "=&r"))]
""
"#"
- "reload_completed"
+ "&& reload_completed"
[(set (match_dup 3) (match_dup 4))
(parallel
[(set (match_dup 4)
@@ -12073,7 +12073,7 @@ (define_insn_and_split "ix86_rotr<dwi>3_doubleword"
(clobber (match_scratch:DWIH 3 "=&r"))]
""
"#"
- "reload_completed"
+ "&& reload_completed"
[(set (match_dup 3) (match_dup 4))
(parallel
[(set (match_dup 4)
@@ -14308,7 +14308,7 @@ (define_insn_and_split "ctz<mode>2"
return "bsf{<imodesuffix>}\t{%1, %0|%0, %1}";
}
- "(TARGET_BMI || TARGET_GENERIC)
+ "&& (TARGET_BMI || TARGET_GENERIC)
&& TARGET_AVOID_FALSE_DEP_FOR_BMI && epilogue_completed
&& optimize_function_for_speed_p (cfun)
&& !reg_mentioned_p (operands[0], operands[1])"
@@ -15712,7 +15712,7 @@ (define_insn_and_split "*load_tp_x32_zext"
(unspec:SI [(const_int 0)] UNSPEC_TP)))]
"TARGET_X32"
"#"
- ""
+ "&& 1"
[(set (match_dup 0)
(zero_extend:DI (match_dup 1)))]
{
@@ -15750,7 +15750,7 @@ (define_insn_and_split "*add_tp_x32_zext"
(clobber (reg:CC FLAGS_REG))]
"TARGET_X32"
"#"
- ""
+ "&& 1"
[(parallel
[(set (match_dup 0)
(zero_extend:DI
@@ -15841,7 +15841,7 @@ (define_insn_and_split "*tls_dynamic_gnu2_combine_32"
(clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT && TARGET_GNU2_TLS"
"#"
- ""
+ "&& 1"
[(set (match_dup 0) (match_dup 5))]
{
operands[5] = can_create_pseudo_p () ? gen_reg_rtx (Pmode) : operands[0];
@@ -15900,7 +15900,7 @@ (define_insn_and_split "*tls_dynamic_gnu2_combine_64_<mode>"
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && TARGET_GNU2_TLS"
"#"
- ""
+ "&& 1"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = can_create_pseudo_p () ? gen_reg_rtx (ptr_mode) : operands[0];
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 4c2b724..e6737b1 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -1668,7 +1668,7 @@ (define_insn_and_split "mmx_pack<s_trunsuffix>swb"
pack<s_trunsuffix>swb\t{%2, %0|%0, %2}
#
#"
- "TARGET_SSE2 && reload_completed
+ "&& TARGET_SSE2 && reload_completed
&& SSE_REGNO_P (REGNO (operands[0]))"
[(const_int 0)]
"ix86_split_mmx_pack (operands, <any_s_truncate:CODE>); DONE;"
@@ -1688,7 +1688,7 @@ (define_insn_and_split "mmx_packssdw"
packssdw\t{%2, %0|%0, %2}
#
#"
- "TARGET_SSE2 && reload_completed
+ "&& TARGET_SSE2 && reload_completed
&& SSE_REGNO_P (REGNO (operands[0]))"
[(const_int 0)]
"ix86_split_mmx_pack (operands, SS_TRUNCATE); DONE;"
@@ -1711,7 +1711,7 @@ (define_insn_and_split "mmx_punpckhbw"
punpckhbw\t{%2, %0|%0, %2}
#
#"
- "TARGET_SSE2 && reload_completed
+ "&& TARGET_SSE2 && reload_completed
&& SSE_REGNO_P (REGNO (operands[0]))"
[(const_int 0)]
"ix86_split_mmx_punpck (operands, true); DONE;"
@@ -1734,7 +1734,7 @@ (define_insn_and_split "mmx_punpcklbw"
punpcklbw\t{%2, %0|%0, %k2}
#
#"
- "TARGET_SSE2 && reload_completed
+ "&& TARGET_SSE2 && reload_completed
&& SSE_REGNO_P (REGNO (operands[0]))"
[(const_int 0)]
"ix86_split_mmx_punpck (operands, false); DONE;"
@@ -1755,7 +1755,7 @@ (define_insn_and_split "mmx_punpckhwd"
punpckhwd\t{%2, %0|%0, %2}
#
#"
- "TARGET_SSE2 && reload_completed
+ "&& TARGET_SSE2 && reload_completed
&& SSE_REGNO_P (REGNO (operands[0]))"
[(const_int 0)]
"ix86_split_mmx_punpck (operands, true); DONE;"
@@ -1776,7 +1776,7 @@ (define_insn_and_split "mmx_punpcklwd"
punpcklwd\t{%2, %0|%0, %k2}
#
#"
- "TARGET_SSE2 && reload_completed
+ "&& TARGET_SSE2 && reload_completed
&& SSE_REGNO_P (REGNO (operands[0]))"
[(const_int 0)]
"ix86_split_mmx_punpck (operands, false); DONE;"
@@ -1797,7 +1797,7 @@ (define_insn_and_split "mmx_punpckhdq"
punpckhdq\t{%2, %0|%0, %2}
#
#"
- "TARGET_SSE2 && reload_completed
+ "&& TARGET_SSE2 && reload_completed
&& SSE_REGNO_P (REGNO (operands[0]))"
[(const_int 0)]
"ix86_split_mmx_punpck (operands, true); DONE;"
@@ -1818,7 +1818,7 @@ (define_insn_and_split "mmx_punpckldq"
punpckldq\t{%2, %0|%0, %k2}
#
#"
- "TARGET_SSE2 && reload_completed
+ "&& TARGET_SSE2 && reload_completed
&& SSE_REGNO_P (REGNO (operands[0]))"
[(const_int 0)]
"ix86_split_mmx_punpck (operands, false); DONE;"
@@ -2542,7 +2542,7 @@ (define_insn_and_split "mmx_pmovmskb"
"@
pmovmskb\t{%1, %0|%0, %1}
#"
- "TARGET_SSE2 && reload_completed
+ "&& TARGET_SSE2 && reload_completed
&& SSE_REGNO_P (REGNO (operands[1]))"
[(set (match_dup 0)
(unspec:SI [(match_dup 1)] UNSPEC_MOVMSK))
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 9d3728d..9919cc0 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -5223,7 +5223,7 @@ (define_insn_and_split "sse_cvtpi2ps"
cvtpi2ps\t{%2, %0|%0, %2}
#
#"
- "TARGET_SSE2 && reload_completed
+ "&& TARGET_SSE2 && reload_completed
&& SSE_REG_P (operands[2])"
[(const_int 0)]
{
@@ -5278,7 +5278,7 @@ (define_insn_and_split "sse_cvtps2pi"
"@
cvtps2pi\t{%1, %0|%0, %q1}
#"
- "TARGET_SSE2 && reload_completed
+ "&& TARGET_SSE2 && reload_completed
&& SSE_REG_P (operands[0])"
[(const_int 0)]
{
@@ -5310,7 +5310,7 @@ (define_insn_and_split "sse_cvttps2pi"
"@
cvttps2pi\t{%1, %0|%0, %q1}
#"
- "TARGET_SSE2 && reload_completed
+ "&& TARGET_SSE2 && reload_completed
&& SSE_REG_P (operands[0])"
[(const_int 0)]
{
@@ -16467,7 +16467,7 @@ (define_insn_and_split "*<sse2_avx2>_pmovmskb_lt"
UNSPEC_MOVMSK))]
"TARGET_SSE2"
"#"
- ""
+ "&& 1"
[(set (match_dup 0)
(unspec:SI [(match_dup 1)] UNSPEC_MOVMSK))]
""
@@ -16489,7 +16489,7 @@ (define_insn_and_split "*<sse2_avx2>_pmovmskb_zext_lt"
UNSPEC_MOVMSK)))]
"TARGET_64BIT && TARGET_SSE2"
"#"
- ""
+ "&& 1"
[(set (match_dup 0)
(zero_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_MOVMSK)))]
""
@@ -16511,7 +16511,7 @@ (define_insn_and_split "*sse2_pmovmskb_ext_lt"
UNSPEC_MOVMSK)))]
"TARGET_64BIT && TARGET_SSE2"
"#"
- ""
+ "&& 1"
[(set (match_dup 0)
(sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_MOVMSK)))]
""
@@ -16692,7 +16692,7 @@ (define_insn_and_split "ssse3_ph<plusminus_mnemonic>wv4hi3"
ph<plusminus_mnemonic>w\t{%2, %0|%0, %2}
#
#"
- "TARGET_SSSE3 && reload_completed
+ "&& TARGET_SSSE3 && reload_completed
&& SSE_REGNO_P (REGNO (operands[0]))"
[(const_int 0)]
{
@@ -16777,7 +16777,7 @@ (define_insn_and_split "ssse3_ph<plusminus_mnemonic>dv2si3"
ph<plusminus_mnemonic>d\t{%2, %0|%0, %2}
#
#"
- "TARGET_SSSE3 && reload_completed
+ "&& TARGET_SSSE3 && reload_completed
&& SSE_REGNO_P (REGNO (operands[0]))"
[(const_int 0)]
{
@@ -17185,7 +17185,7 @@ (define_insn_and_split "*ssse3_pshufbv8qi3"
pshufb\t{%2, %0|%0, %2}
#
#"
- "TARGET_SSSE3 && reload_completed
+ "&& TARGET_SSSE3 && reload_completed
&& SSE_REGNO_P (REGNO (operands[0]))"
[(set (match_dup 3)
(and:V4SI (match_dup 3) (match_dup 2)))
@@ -17315,7 +17315,7 @@ (define_insn_and_split "ssse3_palignrdi"
gcc_unreachable ();
}
}
- "TARGET_SSSE3 && reload_completed
+ "&& TARGET_SSSE3 && reload_completed
&& SSE_REGNO_P (REGNO (operands[0]))"
[(set (match_dup 0)
(lshiftrt:V1TI (match_dup 0) (match_dup 3)))]
@@ -17769,7 +17769,7 @@ (define_insn_and_split "*<sse4_1_avx2>_pblendvb_lt"
UNSPEC_BLENDV))]
"TARGET_SSE4_1"
"#"
- ""
+ "&& 1"
[(set (match_dup 0)
(unspec:VI1_AVX2
[(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_BLENDV))]
-------------- next part --------------
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 3f59b544f6a..feeeaffcc35 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -6752,7 +6752,7 @@ (define_insn_and_split "*and<mode>3_internal"
return "#";
}
- "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
+ "&& reload_completed && int_reg_operand (operands[0], <MODE>mode)"
[(const_int 0)]
{
rs6000_split_logical (operands, AND, false, false, false);
@@ -6788,7 +6788,7 @@ (define_insn_and_split "*bool<mode>3_internal"
return "#";
}
- "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
+ "&& reload_completed && int_reg_operand (operands[0], <MODE>mode)"
[(const_int 0)]
{
rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, false);
@@ -6825,7 +6825,7 @@ (define_insn_and_split "*boolc<mode>3_internal1"
return "#";
}
- "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
+ "&& (TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
&& reload_completed && int_reg_operand (operands[0], <MODE>mode)"
[(const_int 0)]
{
@@ -6854,7 +6854,7 @@ (define_insn_and_split "*boolc<mode>3_internal2"
(match_operand:TI2 1 "int_reg_operand" "r,r,0")]))]
"!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
"#"
- "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
+ "&& reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
[(const_int 0)]
{
rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, true);
@@ -6885,7 +6885,7 @@ (define_insn_and_split "*boolcc<mode>3_internal1"
return "#";
}
- "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
+ "&& (TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
&& reload_completed && int_reg_operand (operands[0], <MODE>mode)"
[(const_int 0)]
{
@@ -6915,7 +6915,7 @@ (define_insn_and_split "*boolcc<mode>3_internal2"
(match_operand:TI2 2 "int_reg_operand" "r,r,0"))]))]
"!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
"#"
- "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
+ "&& reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
[(const_int 0)]
{
rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true);
@@ -6943,7 +6943,7 @@ (define_insn_and_split "*eqv<mode>3_internal1"
return "#";
}
- "TARGET_P8_VECTOR && reload_completed
+ "&& TARGET_P8_VECTOR && reload_completed
&& int_reg_operand (operands[0], <MODE>mode)"
[(const_int 0)]
{
@@ -6972,7 +6972,7 @@ (define_insn_and_split "*eqv<mode>3_internal2"
(match_operand:TI2 2 "int_reg_operand" "r,r,0"))))]
"!TARGET_P8_VECTOR"
"#"
- "reload_completed && !TARGET_P8_VECTOR"
+ "&& reload_completed && !TARGET_P8_VECTOR"
[(const_int 0)]
{
rs6000_split_logical (operands, XOR, true, false, false);
@@ -7000,7 +7000,7 @@ (define_insn_and_split "one_cmpl<mode>2"
return "#";
}
- "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
+ "&& reload_completed && int_reg_operand (operands[0], <MODE>mode)"
[(const_int 0)]
{
rs6000_split_logical (operands, NOT, false, false, false);
@@ -13532,7 +13532,7 @@ (define_insn_and_split "@eh_set_lr_<mode>"
(clobber (match_scratch:P 1 "=&b"))]
""
"#"
- "reload_completed"
+ "&& reload_completed"
[(const_int 0)]
{
rs6000_emit_eh_reg_restore (operands[0], operands[1]);
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index bcb92be2f5c..2e0abb27354 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1630,7 +1630,7 @@ (define_insn_and_split "vsx_mul_v2di"
UNSPEC_VSX_MULSD))]
"VECTOR_MEM_VSX_P (V2DImode)"
"#"
- "VECTOR_MEM_VSX_P (V2DImode) && !reload_completed"
+ "&& VECTOR_MEM_VSX_P (V2DImode) && !reload_completed"
[(const_int 0)]
{
rtx op0 = operands[0];
@@ -1685,7 +1685,7 @@ (define_insn_and_split "vsx_div_v2di"
UNSPEC_VSX_DIVSD))]
"VECTOR_MEM_VSX_P (V2DImode)"
"#"
- "VECTOR_MEM_VSX_P (V2DImode) && !reload_completed"
+ "&& VECTOR_MEM_VSX_P (V2DImode) && !reload_completed"
[(const_int 0)]
{
rtx op0 = operands[0];
@@ -1732,7 +1732,7 @@ (define_insn_and_split "vsx_udiv_v2di"
UNSPEC_VSX_DIVUD))]
"VECTOR_MEM_VSX_P (V2DImode)"
"#"
- "VECTOR_MEM_VSX_P (V2DImode) && !reload_completed"
+ "&& VECTOR_MEM_VSX_P (V2DImode) && !reload_completed"
[(const_int 0)]
{
rtx op0 = operands[0];
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