[PATCH 0/2] RISC-V: Add ldr/str instruction for T-HEAD.

[Palmer Dabbelt]

On Sat, 10 Jul 2021 19:31:20 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
> Hi,
>
> 	Ping.
>
> 	@Jim @kito
>
> — Jojo
> 在 2021年7月9日 +0800 AM9:30，ALO <rjiejie@linux.alibaba.com>，写道：
>> Hi,
>> 	Ping.
>>
>> — Jojo
>> 在 2021年6月29日 +0800 PM4:11，Jojo R <rjiejie@linux.alibaba.com>，写道：
>> > T-HEAD extends some customized ISAs for Cores.
>> > The patches support ldr/str insns, it likes arm's LDR insn, the
>> > memory model is a base register indexed by (optionally scaled) register.

Sorry about that.  I'd seem some discussion here, but I guess it wasn't 
on the lists and wasn't really a review anyway.  I've taken a 
preliminary look and have a few questions, they're in the patches.

Thanks!