[PATCH 1/2] RISC-V: Add arch flags for T-HEAD.

[Palmer Dabbelt]

On Tue, 29 Jun 2021 01:11:06 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
> 	gcc/
> 	* gcc/config/riscv/riscv.opt (riscv_x_subext): New.
> 	* gcc/config/riscv/riscv-opts.h (MASK_XTHEAD_C): New.
> 	(TARGET_XTHEAD_C): Likewise.
> 	* gcc/common/config/riscv/riscv-common.c
> 	(riscv_ext_flag_table): Use riscv_x_subext & MASK_XTHEAD_C.
> ---
>  gcc/common/config/riscv/riscv-common.c | 2 ++
>  gcc/config/riscv/riscv-opts.h          | 3 +++
>  gcc/config/riscv/riscv.opt             | 3 +++
>  3 files changed, 8 insertions(+)
>
> diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
> index 10868fd417dc..a62080129259 100644
> --- a/gcc/common/config/riscv/riscv-common.c
> +++ b/gcc/common/config/riscv/riscv-common.c
> @@ -906,6 +906,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
>    {"zicsr",    &gcc_options::x_riscv_zi_subext, MASK_ZICSR},
>    {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI},
>
> +  {"xtheadc", &gcc_options::x_riscv_x_subext, MASK_XTHEAD_C},
> +

Is there are documentation as to what this "theadc" extension is?  My 
main worry here would be trickling in instructions under the same custom 
extension, as that will quickly get confusing for users.  If you really 
just have one instruction in this extension that's fine, but if there 
are lots (as the marketing material seems to indicate) then I'd prefer 
to at least have a complete picture first.

Also, having the documentation will be necessary for anyone to actually 
use these instructions.

>    {NULL, NULL, 0}
>  };
>
> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
> index f4cf6ca4b823..a2d84a66f037 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -73,4 +73,7 @@ enum stack_protector_guard {
>  #define TARGET_ZICSR    ((riscv_zi_subext & MASK_ZICSR) != 0)
>  #define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0)
>
> +#define MASK_XTHEAD_C (1 << 0)
> +#define TARGET_XTHEAD_C ((riscv_x_subext & MASK_XTHEAD_C) != 0)
> +
>  #endif /* ! GCC_RISCV_OPTS_H */
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index 5ff85c214307..84176aea05e9 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -195,6 +195,9 @@ long riscv_stack_protector_guard_offset = 0
>  TargetVariable
>  int riscv_zi_subext
>
> +TargetVariable
> +int riscv_x_subext
> +
>  Enum
>  Name(isa_spec_class) Type(enum riscv_isa_spec_class)
>  Supported ISA specs (for use with the -misa-spec= option):