[PATCH v3 6/6] RISC-V: Fix matches against subreg with a bytenum of 0 in riscv.md
Kito Cheng
kito.cheng@gmail.com
Thu Feb 25 02:46:22 GMT 2021
Hi Jim:
Could you take a look for this patch,
I am not sure it's the right change or not for big-endian,
On Thu, Feb 25, 2021 at 6:39 AM Marcus Comstedt <marcus@mc.pp.se> wrote:
>
> These all intend the least significant subpart of the register.
> Use the same endian-neutral "subreg_lowpart_operator" predicate that
> ARM does instead.
>
> gcc/
> * config/riscv/predicates.md (subreg_lowpart_operator): New predicate
> * config/riscv/riscv.md (*addsi3_extended2, *subsi3_extended2)
> (*negsi2_extended2, *mulsi3_extended2, *<optab>si3_mask)
> (*<optab>si3_mask_1, *<optab>di3_mask, *<optab>di3_mask_1)
> (*<optab>si3_extend_mask, *<optab>si3_extend_mask_1): Use
> new predicate "subreg_lowpart_operator"
> ---
> gcc/config/riscv/predicates.md | 5 +++
> gcc/config/riscv/riscv.md | 70 +++++++++++++++++-----------------
> 2 files changed, 40 insertions(+), 35 deletions(-)
>
> diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
> index ef821add663..23211513554 100644
> --- a/gcc/config/riscv/predicates.md
> +++ b/gcc/config/riscv/predicates.md
> @@ -198,6 +198,11 @@
> (define_predicate "signed_order_operator"
> (match_code "eq,ne,lt,le,ge,gt"))
>
> +(define_predicate "subreg_lowpart_operator"
> + (ior (match_code "truncate")
> + (and (match_code "subreg")
> + (match_test "subreg_lowpart_p (op)"))))
> +
> (define_predicate "fp_native_comparison"
> (match_code "eq,lt,le,gt,ge"))
>
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index fcdcc3abaa0..c3687d57047 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -480,9 +480,9 @@
> (define_insn "*addsi3_extended2"
> [(set (match_operand:DI 0 "register_operand" "=r,r")
> (sign_extend:DI
> - (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" " r,r")
> - (match_operand:DI 2 "arith_operand" " r,I"))
> - 0)))]
> + (match_operator:SI 3 "subreg_lowpart_operator"
> + [(plus:DI (match_operand:DI 1 "register_operand" " r,r")
> + (match_operand:DI 2 "arith_operand" " r,I"))])))]
> "TARGET_64BIT"
> "add%i2w\t%0,%1,%2"
> [(set_attr "type" "arith")
> @@ -536,9 +536,9 @@
> (define_insn "*subsi3_extended2"
> [(set (match_operand:DI 0 "register_operand" "= r")
> (sign_extend:DI
> - (subreg:SI (minus:DI (match_operand:DI 1 "reg_or_0_operand" " rJ")
> - (match_operand:DI 2 "register_operand" " r"))
> - 0)))]
> + (match_operator:SI 3 "subreg_lowpart_operator"
> + [(minus:DI (match_operand:DI 1 "reg_or_0_operand" " rJ")
> + (match_operand:DI 2 "register_operand" " r"))])))]
> "TARGET_64BIT"
> "subw\t%0,%z1,%2"
> [(set_attr "type" "arith")
> @@ -572,8 +572,8 @@
> (define_insn "*negsi2_extended2"
> [(set (match_operand:DI 0 "register_operand" "=r")
> (sign_extend:DI
> - (subreg:SI (neg:DI (match_operand:DI 1 "register_operand" " r"))
> - 0)))]
> + (match_operator:SI 2 "subreg_lowpart_operator"
> + [(neg:DI (match_operand:DI 1 "register_operand" " r"))])))]
> "TARGET_64BIT"
> "negw\t%0,%1"
> [(set_attr "type" "arith")
> @@ -627,9 +627,9 @@
> (define_insn "*mulsi3_extended2"
> [(set (match_operand:DI 0 "register_operand" "=r")
> (sign_extend:DI
> - (subreg:SI (mult:DI (match_operand:DI 1 "register_operand" " r")
> - (match_operand:DI 2 "register_operand" " r"))
> - 0)))]
> + (match_operator:SI 3 "subreg_lowpart_operator"
> + [(mult:DI (match_operand:DI 1 "register_operand" " r")
> + (match_operand:DI 2 "register_operand" " r"))])))]
> "TARGET_MUL && TARGET_64BIT"
> "mulw\t%0,%1,%2"
> [(set_attr "type" "imul")
> @@ -1591,10 +1591,10 @@
> [(set (match_operand:SI 0 "register_operand" "= r")
> (any_shift:SI
> (match_operand:SI 1 "register_operand" " r")
> - (subreg:QI
> - (and:SI
> - (match_operand:SI 2 "register_operand" "r")
> - (match_operand 3 "const_int_operand")) 0)))]
> + (match_operator 4 "subreg_lowpart_operator"
> + [(and:SI
> + (match_operand:SI 2 "register_operand" "r")
> + (match_operand 3 "const_int_operand"))])))]
> "(INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
> == GET_MODE_BITSIZE (SImode)-1"
> "#"
> @@ -1610,10 +1610,10 @@
> [(set (match_operand:SI 0 "register_operand" "= r")
> (any_shift:SI
> (match_operand:SI 1 "register_operand" " r")
> - (subreg:QI
> - (and:DI
> - (match_operand:DI 2 "register_operand" "r")
> - (match_operand 3 "const_int_operand")) 0)))]
> + (match_operator 4 "subreg_lowpart_operator"
> + [(and:DI
> + (match_operand:DI 2 "register_operand" "r")
> + (match_operand 3 "const_int_operand"))])))]
> "TARGET_64BIT
> && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
> == GET_MODE_BITSIZE (SImode)-1"
> @@ -1646,10 +1646,10 @@
> [(set (match_operand:DI 0 "register_operand" "= r")
> (any_shift:DI
> (match_operand:DI 1 "register_operand" " r")
> - (subreg:QI
> - (and:SI
> - (match_operand:SI 2 "register_operand" "r")
> - (match_operand 3 "const_int_operand")) 0)))]
> + (match_operator 4 "subreg_lowpart_operator"
> + [(and:SI
> + (match_operand:SI 2 "register_operand" "r")
> + (match_operand 3 "const_int_operand"))])))]
> "TARGET_64BIT
> && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode)-1))
> == GET_MODE_BITSIZE (DImode)-1"
> @@ -1666,10 +1666,10 @@
> [(set (match_operand:DI 0 "register_operand" "= r")
> (any_shift:DI
> (match_operand:DI 1 "register_operand" " r")
> - (subreg:QI
> - (and:DI
> - (match_operand:DI 2 "register_operand" "r")
> - (match_operand 3 "const_int_operand")) 0)))]
> + (match_operator 4 "subreg_lowpart_operator"
> + [(and:DI
> + (match_operand:DI 2 "register_operand" "r")
> + (match_operand 3 "const_int_operand"))])))]
> "TARGET_64BIT
> && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode)-1))
> == GET_MODE_BITSIZE (DImode)-1"
> @@ -1702,10 +1702,10 @@
> (sign_extend:DI
> (any_shift:SI
> (match_operand:SI 1 "register_operand" " r")
> - (subreg:QI
> - (and:SI
> - (match_operand:SI 2 "register_operand" " r")
> - (match_operand 3 "const_int_operand")) 0))))]
> + (match_operator 4 "subreg_lowpart_operator"
> + [(and:SI
> + (match_operand:SI 2 "register_operand" " r")
> + (match_operand 3 "const_int_operand"))]))))]
> "TARGET_64BIT
> && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
> == GET_MODE_BITSIZE (SImode)-1"
> @@ -1724,10 +1724,10 @@
> (sign_extend:DI
> (any_shift:SI
> (match_operand:SI 1 "register_operand" " r")
> - (subreg:QI
> - (and:DI
> - (match_operand:DI 2 "register_operand" " r")
> - (match_operand 3 "const_int_operand")) 0))))]
> + (match_operator 4 "subreg_lowpart_operator"
> + [(and:DI
> + (match_operand:DI 2 "register_operand" " r")
> + (match_operand 3 "const_int_operand"))]))))]
> "TARGET_64BIT
> && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
> == GET_MODE_BITSIZE (SImode)-1"
> --
> 2.26.2
>
More information about the Gcc-patches
mailing list