[PATCH] aarch64: Use RTL builtins for [su]mull_high_lane[q] intrinsics
Jonathan Wright
Jonathan.Wright@arm.com
Thu Feb 4 13:29:33 GMT 2021
Hi,
As subject this patch rewrites [su]mull_high_lane[q] Neon intrinsics to use RTL
builtins rather than inline assembly code, allowing for better scheduling and
optimization.
Regression tested and bootstrapped on aarch64-none-linux-gnu and
aarch64_be-none-elf - no issues.
Ok for master?
Thanks,
Jonathan
---
gcc/ChangeLog:
2021-02-03 Jonathan Wright <jonathan.wright@arm.com>
* config/aarch64/aarch64-simd-builtins.def: Add
[su]mull_hi_lane[q] builtin generator macros.
* config/aarch64/aarch64-simd.md
(aarch64_<su>mull_hi_lane<mode>_insn): Define.
(aarch64_<su>mull_hi_lane<mode>): Define.
(aarch64_<su>mull_hi_laneq<mode>_insn): Define.
(aarch64_<su>mull_hi_laneq<mode>): Define.
* config/aarch64/arm_neon.h (vmull_high_lane_s16): Use RTL
builtin instead of inline asm.
(vmull_high_lane_s32): Likewise.
(vmull_high_lane_u16): Likewise.
(vmull_high_lane_u32): Likewise.
(vmull_high_laneq_s16): Likewise.
(vmull_high_laneq_s32): Likewise.
(vmull_high_laneq_u16): Likewise.
(vmull_high_laneq_u32): Liekwise.
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