[PATCH] PR target/98743: Fix ICE in convert_move for RISC-V
Kito Cheng
kito.cheng@sifive.com
Mon Feb 1 09:38:46 GMT 2021
- Check `TO` mode is not BLMmode before call store_expr, calling store_expr
with BLKmode will cause ICE.
- Verified with riscv64, x86_64 and aarch64, no introduce new regression.
Note: Those logic was introduced by 3e60ddeb8220ed388819bb3f14e8caa9309fd3c2,
so I cc Jakub for reivew.
gcc/ChangeLog:
PR target/98743
* expr.c: Check mode before calling store_expr.
gcc/testsuite/ChangeLog:
PR target/98743
* g++.target/riscv/pr98743.C: New.
---
gcc/expr.c | 1 +
gcc/testsuite/g++.target/riscv/pr98743.C | 27 ++++++++++++++++++++++++
2 files changed, 28 insertions(+)
create mode 100644 gcc/testsuite/g++.target/riscv/pr98743.C
diff --git a/gcc/expr.c b/gcc/expr.c
index 04ef5ad114d..3cf492acea3 100644
--- a/gcc/expr.c
+++ b/gcc/expr.c
@@ -5459,6 +5459,7 @@ expand_assignment (tree to, tree from, bool nontemporal)
/* If to_rtx is a promoted subreg, we need to zero or sign
extend the value afterwards. */
if (TREE_CODE (to) == MEM_REF
+ && mode != BLKmode
&& !REF_REVERSE_STORAGE_ORDER (to)
&& known_eq (bitpos, 0)
&& known_eq (bitsize, GET_MODE_BITSIZE (GET_MODE (to_rtx))))
diff --git a/gcc/testsuite/g++.target/riscv/pr98743.C b/gcc/testsuite/g++.target/riscv/pr98743.C
new file mode 100644
index 00000000000..1b94597ac68
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/pr98743.C
@@ -0,0 +1,27 @@
+// Test for value-initialization via {}
+// { dg-do run { target c++11 } }
+/* { dg-options "-Og -version -fno-early-inlining -finline-small-functions -fpack-struct" */
+void * operator new (__SIZE_TYPE__, void *p) { return p; }
+void * operator new[] (__SIZE_TYPE__, void *p) { return p; }
+
+// Empty base so A isn't an aggregate
+struct B {};
+struct A: B {
+ int i;
+};
+
+struct C: A {
+ C(): A{} {}
+};
+
+int main()
+{
+ int space = 42;
+ A* ap = new (&space) A{};
+ int space1[1] = { 42 };
+ A* a1p = new (space1) A[1]{};
+ if (ap->i != 0 ||
+ a1p[0].i != 0)
+ return 1;
+ return 0;
+}
--
2.30.0
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