[PATCH 1/2] RISC-V: Add arch flags for T-HEAD.

Jojo R rjiejie@linux.alibaba.com
Fri Aug 27 03:22:59 GMT 2021


	- Add documents of XuanTie series [1].
	- Add QEMU binary [2] by now, you can execute application with argument ‘-cpu c910’,
	   and opening source is on the way.
	- Add my colleague [3] to commit patches of binutils

[1] https://github.com/rjiejie/XuanTie-doc
[2] https://github.com/rjiejie/thead-bin-qemu
[3] lifang_xia@c-sky.com


— Jojo
在 2021年7月22日 +0800 AM10:16,Jojo R <rjiejie@linux.alibaba.com>,写道:
> — Jojo
> 在 2021年7月22日 +0800 AM4:53,Jim Wilson <jimw@sifive.com>,写道:
> > On Tue, Jul 13, 2021 at 11:06 AM Palmer Dabbelt <palmer@dabbelt.com> wrote:
> > > Is there are documentation as to what this "theadc" extension is?
> >
> > The best doc I know of is    https://github.com/isrc-cas/c910-llvmThe README is in Chinese, but google translate does a decent job on it.  If you want more details, you have to read the llvm sources to see exactly what each instruction does.  They have mentioned that they are working on English language docs, but I don't know when they will be available.
> > There are quite a few T-Head specific instructions here.  This patch is only adding support for a few of them, probably as a trial to see how it goes before they try to add the rest.
> Hi,
> 	Please let me feed more details for this patch,
> 	There are about ~100+ instructions in our ISA spec,
> 	and we put the RFC[1] to ask guide how to commit vendor extension ISAs,
> 	we want to commit one type instruction every time, it’s helpful for reviewing.
> 	Some Chinese T-HEAD ISA Specs have been on the our web page [2] already,
> 	and we are converting these docs to english version to help your reading :)
> 	it will be out in the next week, including binutils.
> 	Thanks for your suggestion of the patch
> [1] https://github.com/riscv/riscv-gcc/issues/278
> [2] https://www.t-head.cn/technology
> > Jim
> >

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