[PATCH 1/2, rs6000] int128 sign extention instructions (partial prereq)

[Segher Boessenkool]

Hi!

On Thu, Sep 24, 2020 at 10:59:09AM -0500, will schmidt wrote:
>   This is a sub-set of the 128-bit sign extension support patch series
> that I believe will be fully implemented in a subsequent patch from Carl.
> This is a necessary pre-requisite for the vector-load/store rightmost
> element patch that follows in this thread.

> 	* config/rs6000/rs6000.md (enum c_enum): Add UNSPEC_EXTENDDITI2
> 	and UNSPEC_MTVSRD_DITI_W1 entries.

(The define_c_enum is called "unspec", not "c_enum".)

These should really be coded not as unspecs, but as normal RTL code?
That way, it can be optimised.

> +;; Move DI value from GPR to TI mode in VSX register, word 1.
> +(define_insn "mtvsrdd_diti_w1"
> +  [(set (match_operand:TI 0 "register_operand" "=wa")
> +	(unspec:TI [(match_operand:DI 1 "register_operand" "r")]
> +		   UNSPEC_MTVSRD_DITI_W1))]
> +  "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
> +  "mtvsrdd %x0,0,%1"
> +  [(set_attr "type" "vecsimple")])

(Hrm, we should have had an extended mnemonic for this, "mtvsrld".  Oh
well.)

This should be in vsx.md?

And, please just extend vsx_concat for this?  Maybe using
reg_or_zero_operand?

> +;; Sign extend 64-bit value in TI reg, word 1, to 128-bit value in TI reg
> +(define_insn "extendditi2_vector"
> +  [(set (match_operand:TI 0 "gpc_reg_operand" "=v")
> +        (unspec:TI [(match_operand:TI 1 "gpc_reg_operand" "v")]
> +         UNSPEC_EXTENDDITI2))]
> +  "TARGET_POWER10"
> +  "vextsd2q %0,%1"
> +  [(set_attr "type" "exts")])

This should use something with sign_extend.

Okay for trunk.  Thanks!  But the unspecs really need to go sooner
rather than later (these are by far not the only ones, so :-( ).


Segher