[PATCH] x86: Require MMX for __builtin_ia32_maskmovq

[H.J. Lu]

Since "MASKMOVQ mm1, mm2" is an SSE instruction which requires MMX and
MMX/SSE ISAs are handled separately, make __builtin_ia32_maskmovq require
MMX instead of SSE.

gcc/

	PR target/97140
	* config/i386/i386-expand.c (ix86_expand_builtin): Require MMX
	for __builtin_ia32_maskmovq.
	* config/i386/mmx.md (mmx_maskmovq): Replace TARGET_SSE with
	TARGET_MMX.
	(*mmx_maskmovq): Likewise.

gcc/testsuite/

	PR target/97140
	* gcc.target/i386/pr97140.c: New test.
---
 gcc/config/i386/i386-expand.c           |  6 +++++-
 gcc/config/i386/mmx.md                  |  4 ++--
 gcc/testsuite/gcc.target/i386/pr97140.c | 10 ++++++++++
 3 files changed, 17 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/pr97140.c

diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c
index e6f8b314f18..e6285cf592e 100644
--- a/gcc/config/i386/i386-expand.c
+++ b/gcc/config/i386/i386-expand.c
@@ -10982,7 +10982,11 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget,
        == (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4))
       && (isa & (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4)) != 0)
     isa |= (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4);
-  if ((bisa & OPTION_MASK_ISA_MMX) && !TARGET_MMX && TARGET_MMX_WITH_SSE)
+  /* NB: __builtin_ia32_maskmovq requires MMX.  */
+  if (fcode != IX86_BUILTIN_MASKMOVQ
+      && (bisa & OPTION_MASK_ISA_MMX)
+      && !TARGET_MMX
+      && TARGET_MMX_WITH_SSE)
     {
       bisa &= ~OPTION_MASK_ISA_MMX;
       bisa |= OPTION_MASK_ISA_SSE2;
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 7c9640d4f9f..610e4b591f7 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -2549,7 +2549,7 @@ (define_expand "mmx_maskmovq"
 		      (match_operand:V8QI 2 "register_operand")
 		      (match_dup 0)]
 		     UNSPEC_MASKMOV))]
-  "TARGET_SSE || TARGET_3DNOW_A")
+  "TARGET_MMX || TARGET_3DNOW_A")
 
 (define_insn "*mmx_maskmovq"
   [(set (mem:V8QI (match_operand:P 0 "register_operand" "D"))
@@ -2557,7 +2557,7 @@ (define_insn "*mmx_maskmovq"
 		      (match_operand:V8QI 2 "register_operand" "y")
 		      (mem:V8QI (match_dup 0))]
 		     UNSPEC_MASKMOV))]
-  "TARGET_SSE || TARGET_3DNOW_A"
+  "TARGET_MMX || TARGET_3DNOW_A"
   ;; @@@ check ordering of operands in intel/nonintel syntax
   "maskmovq\t{%2, %1|%1, %2}"
   [(set_attr "type" "mmxcvt")
diff --git a/gcc/testsuite/gcc.target/i386/pr97140.c b/gcc/testsuite/gcc.target/i386/pr97140.c
new file mode 100644
index 00000000000..edb39d916ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr97140.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -mno-mmx -Wno-psabi" } */
+
+typedef int __m64 __attribute__ ((__vector_size__ (8), __may_alias__));
+typedef char __v8qi __attribute__ ((__vector_size__ (8)));
+void
+_mm_maskmove_si64 (__m64 __A, __m64 __N, char *__P)
+{
+    __builtin_ia32_maskmovq ((__v8qi)__A, (__v8qi)__N, __P); /* { dg-error "needs isa option -msse -m3dnowa -mmmx" } */
+}
-- 
2.26.2