[committed] MSP430: Support a memory operand for op1 of andneghi3
Jozef Lawrynowicz
jozef.l@mittosystems.com
Tue Oct 20 10:29:34 GMT 2020
The attached patch fixes an ICE caused by an unrecognizeable insn
generated when compiling gcc.c-torture/execute/pr97386-1.c at -O0 for
msp430-elf.
Successfully regtested on trunk and committed as obvious.
-------------- next part --------------
>From 8c3846e80210ba437644b5b91d9bd9c564ca565a Mon Sep 17 00:00:00 2001
From: Jozef Lawrynowicz <jozef.l@mittosystems.com>
Date: Tue, 20 Oct 2020 11:26:20 +0100
Subject: [PATCH] MSP430: Support a memory operand for op1 of andneghi3
This fixes an ICE caused by an unrecognizeable insn generated when
compiling gcc.c-torture/execute/pr97386-1.c at -O0.
gcc/ChangeLog:
* config/msp430/msp430.md (andneghi3): Allow general operand for
op1 and update output assembler template.
---
gcc/config/msp430/msp430.md | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/config/msp430/msp430.md b/gcc/config/msp430/msp430.md
index f70e61b97dd..ad244bb0f33 100644
--- a/gcc/config/msp430/msp430.md
+++ b/gcc/config/msp430/msp430.md
@@ -1346,12 +1346,12 @@ (define_insn "bis_SR"
;; instructions, so we provide a pattern to support it here.
(define_insn "andneghi3"
[(set (match_operand:HI 0 "register_operand" "=r")
- (and:HI (neg:HI (match_operand:HI 1 "register_operand" "r"))
+ (and:HI (neg:HI (match_operand:HI 1 "general_operand" "rm"))
(match_operand 2 "immediate_operand" "n")))]
""
"*
if (REGNO (operands[0]) != REGNO (operands[1]))
- return \"MOV.W\t%1, %0 { INV.W\t%0 { INC.W\t%0 { AND.W\t%2, %0\";
+ return \"MOV%X1.W\t%1, %0 { INV.W\t%0 { INC.W\t%0 { AND.W\t%2, %0\";
else
return \"INV.W\t%0 { INC.W\t%0 { AND.W\t%2, %0\";
"
--
2.28.0
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