[PATCH v2] rs6000, vector integer multiply/divide/modulo instructions

[Pat Haugen]

On 11/24/20 8:17 PM, Pat Haugen via Gcc-patches wrote:
> On 11/24/20 12:59 PM, Carl Love via Gcc-patches wrote:
>> +
>> +(define_insn "dives_<mode>"
>> +  [(set (match_operand:VIlong 0 "vsx_register_operand" "=v")
>> +        (unspec:VIlong [(match_operand:VIlong 1 "vsx_register_operand" "v")
>> +		        (match_operand:VIlong 2 "vsx_register_operand" "v")]
>> +		       UNSPEC_VDIVES))]
>> +  "TARGET_POWER10"
>> +  "vdives<wd> %0,%1,%2"
>> +  [(set_attr "type" "vecdiv")
>> +   (set_attr "size" "128")])
>> +
>> +(define_insn "diveu_<mode>"
>> +  [(set (match_operand:VIlong 0 "vsx_register_operand" "=v")
>> +        (unspec: VIlong [(match_operand:VIlong 1 "vsx_register_operand" "v")
>> +			 (match_operand:VIlong 2 "vsx_register_operand" "v")]
>> +			UNSPEC_VDIVEU))]
>> +  "TARGET_POWER10"
>> +  "vdiveu<wd> %0,%1,%2"
>> +  [(set_attr "type" "vecdiv")
>> +   (set_attr "size" "128")])
>> +
>> +(define_insn "div<mode>3"
>> +  [(set (match_operand:VIlong 0 "vsx_register_operand" "=v")
>> +	(div:VIlong (match_operand:VIlong 1 "vsx_register_operand" "v")
>> +		    (match_operand:VIlong 2 "vsx_register_operand" "v")))]
>> +  "TARGET_POWER10"
>> +  "vdivs<wd> %0,%1,%2"
>> +  [(set_attr "type" "vecdiv")
>> +   (set_attr "size" "128")])
>> +
>> +(define_insn "udiv<mode>3"
>> +  [(set (match_operand:VIlong 0 "vsx_register_operand" "=v")
>> +	(udiv:VIlong (match_operand:VIlong 1 "vsx_register_operand" "v")
>> +		    (match_operand:VIlong 2 "vsx_register_operand" "v")))]
>> +  "TARGET_POWER10"
>> +  "vdivu<wd> %0,%1,%2"
>> +  [(set_attr "type" "vecdiv")
>> +   (set_attr "size" "128")])
>> +
>> +(define_insn "mods_<mode>"
>> +  [(set (match_operand:VIlong 0 "vsx_register_operand" "=v")
>> +	(mod:VIlong (match_operand:VIlong 1 "vsx_register_operand" "v")
>> +		    (match_operand:VIlong 2 "vsx_register_operand" "v")))]
>> +  "TARGET_POWER10"
>> +  "vmods<wd> %0,%1,%2"
>> +  [(set_attr "type" "vecdiv")
>> +   (set_attr "size" "128")])
>> +
>> +(define_insn "modu_<mode>"
>> +  [(set (match_operand:VIlong 0 "vsx_register_operand" "=v")
>> +	(umod:VIlong (match_operand:VIlong 1 "vsx_register_operand" "v")
>> +		     (match_operand:VIlong 2 "vsx_register_operand" "v")))]
>> +  "TARGET_POWER10"
>> +  "vmodu<wd> %0,%1,%2"
>> +  [(set_attr "type" "vecdiv")
>> +   (set_attr "size" "128")])
> 
> We should only be setting "size" "128" for instructions that operate on scalar 128-bit data items (i.e. 'vdivesq' etc). Since the above insns are either V2DI/V4SI (ala VIlong mode_iterator), they shouldn't be marked as size 128. If you want to set the size based on mode, (set_attr "size" "<bits>") should do the trick I believe.

Well, after you update "(define_mode_attr bits" in rs6000.md for V2DI/V4SI.