[PATCH][AArch64] ACLE intrinsics: convert from BFloat16 to Float32

[Richard Sandiford]

Dennis Zhang <dennis.zhang@arm.com> writes:
> Hi Richard,
>
> On 10/29/20 5:48 PM, Richard Sandiford wrote:
>> Dennis Zhang <Dennis.Zhang@arm.com> writes:
>>> diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
>>> index 5bc596dbffc..b68c3ca7f4b 100644
>>> --- a/gcc/config/aarch64/aarch64-simd-builtins.def
>>> +++ b/gcc/config/aarch64/aarch64-simd-builtins.def
>>> @@ -732,3 +732,8 @@
>>>     VAR1 (UNOP, bfcvtn_q, 0, ALL, v8bf)
>>>     VAR1 (BINOP, bfcvtn2, 0, ALL, v8bf)
>>>     VAR1 (UNOP, bfcvt, 0, ALL, bf)
>>> +
>>> +  /* Implemented by aarch64_{v}bfcvt{_high}<mode>.  */
>>> +  VAR2 (UNOP, vbfcvt, 0, ALL, v4bf, v8bf)
>>> +  VAR1 (UNOP, vbfcvt_high, 0, ALL, v8bf)
>>> +  VAR1 (UNOP, bfcvt, 0, ALL, sf)
>> 
>> New intrinsics should use something more specific than “ALL”.
>> Since these functions are pure non-trapping integer operations,
>> I think they should use “AUTO_FP” instead.  (On reflection,
>> we should probably change the name.)
>> 
>>> +(define_insn "aarch64_bfcvtsf"
>>> +  [(set (match_operand:SF 0 "register_operand" "=w")
>>> +	(unspec:SF [(match_operand:BF 1 "register_operand" "w")]
>>> +		    UNSPEC_BFCVT))]
>>> +  "TARGET_BF16_FP"
>>> +  "shl\\t%d0, %d1, #16"
>>> +  [(set_attr "type" "neon_shift_reg")]
>> 
>> I think this should be neon_shift_imm instead.
>> 
>> OK with those changes, thanks.
>> 
>> Richard
>> 
>
> I've fixed the Flag and the insn attribute.
> I will commit it if no further issues.

LGTM, thanks.

Richard