[RFC/PATCH] IFN: Fix mask_{load,store} optab support macros

[Jim Wilson]

On Wed, Jun 24, 2020 at 1:35 AM Richard Sandiford
<richard.sandiford@arm.com> wrote:
> Richard Biener <richard.guenther@gmail.com> writes:
> > AVX512 would have V16SImode and SImode because the mask would have
> > an integer mode?  Likewise I could imagine RISC-V using V4SImode and V4QImode
> > or however their mask registers look like.

RISC-V has 7 mask modes, currently.  Masks are defined to always fit
in one register.  So if you have a register group of 8 (mlen=8) and an
element length of 8-bits (elen=8) then you have 1 bit of mask per
element which completely fills one register.  If you have a register
group of 1 (mlen=1) and an element length of 64-bits (elen=64) then
you have 64-bits of mask per element which completely fills one
register.  So we need a mode for each possible way of tiling a
register with mask bits, which is 2**x for x=(0..6).

> But what I mean is, once you know the vector mode, there should only
> be one “choice” of mask mode.

This is true for RISC-V also.  The mask mode is determined by the
number of registers in the group and the element width, so there is
only one valid mask mode for each vector mode.

Jim