[PATH 3/6] RISC-V: Add vector VLEN and SEW

[戎杰杰(无音)]

gcc/ChangeLog:

        * config/riscv/riscv-c.c (__riscv_vector): Define.
        * config/riscv/riscv-opts.h (riscv_vlen): New.
        * config/riscv/riscv-v.h (TARGET_VECTOR_VLEN): Define.
        (UNITS_PER_VR_REG): Likewise.
        (RISCV_VSEW_T): Likewise.
        * config/riscv/riscv.opt (-mvlen): New.
---
 gcc/config/riscv/riscv-c.c    |  3 +++
 gcc/config/riscv/riscv-opts.h |  6 ++++++
 gcc/config/riscv/riscv-v.h    | 14 ++++++++++++++
 gcc/config/riscv/riscv.opt    | 14 ++++++++++++++
 4 files changed, 37 insertions(+)

diff --git a/gcc/config/riscv/riscv-c.c b/gcc/config/riscv/riscv-c.c
index ca72de74a7b..96a661681bc 100644
--- a/gcc/config/riscv/riscv-c.c
+++ b/gcc/config/riscv/riscv-c.c
@@ -52,6 +52,9 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
   if (TARGET_DIV && TARGET_MUL)
     builtin_define ("__riscv_muldiv");

+  if (TARGET_VECTOR)
+    builtin_define_with_int_value("__riscv_vector", riscv_vlen);
+
   builtin_define_with_int_value ("__riscv_xlen", UNITS_PER_WORD * 8);
   if (TARGET_HARD_FLOAT)
     builtin_define_with_int_value ("__riscv_flen", UNITS_PER_FP_REG * 8);
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index f3031f2e523..87f3abd7826 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -46,4 +46,10 @@ enum riscv_microarchitecture_type {
 };
 extern enum riscv_microarchitecture_type riscv_microarchitecture;

+enum riscv_vlen_bits {
+  VLEN_64 = 64,
+  VLEN_128 = 128
+};
+extern enum riscv_vlen_bits riscv_vlen;
+
 #endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/config/riscv/riscv-v.h b/gcc/config/riscv/riscv-v.h
index 6e193f936a4..c17242b9d47 100755
--- a/gcc/config/riscv/riscv-v.h
+++ b/gcc/config/riscv/riscv-v.h
@@ -22,8 +22,22 @@ along with GCC; see the file COPYING3.  If not see
 #ifndef GCC_RISCV_V_H
 #define GCC_RISCV_V_H

+#define TARGET_VECTOR_VLEN(BITS) (TARGET_VECTOR && riscv_vlen == VLEN_##BITS )
+
 #define V_REG_FIRST 66
 #define V_REG_LAST  97
 #define V_REG_NUM   (V_REG_LAST - V_REG_FIRST + 1)

+#define UNITS_PER_VR_REG (riscv_vlen / 8)
+
+#define VR_REG_P(REGNO)  \
+  ((unsigned int) ((int) (REGNO) - V_REG_FIRST) < V_REG_NUM)
+
+typedef enum {
+    RVV_E8 = 0,
+    RVV_E16,
+    RVV_E32,
+    RVV_E64
+} RISCV_VSEW_T;
+
 #endif
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 436d51faccd..25c5c9d3545 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -62,6 +62,20 @@ Enum(abi_type) String(lp64f) Value(ABI_LP64F)
 EnumValue
 Enum(abi_type) String(lp64d) Value(ABI_LP64D)

+mvlen=
+Target Report RejectNegative Joined Enum(vlen_bits) Var(riscv_vlen) Init(VLEN_128)
+Specify bits of vector register.
+
+Enum
+Name(vlen_bits) Type(enum riscv_vlen_bits)
+Supported VLEN (for use with the -mvlen= option):
+
+EnumValue
+Enum(vlen_bits) String(64) Value(VLEN_64)
+
+EnumValue
+Enum(vlen_bits) String(128) Value(VLEN_128)
+
 mfdiv
 Target Report Mask(FDIV)
 Use hardware floating-point divide and square root instructions.
-- 
2.24.3 (Apple Git-128)