[AArch64] Fix constraints for CPY /M

[Richard Sandiford]

The constraints for CPY /M allowed p0-p15 instead of the intended p0-p7.
This looks like a pasto from the preceding constant pattern, where p0-p15
is allowed.

Tested on aarch64-linux-gnu and applied as 279899.

Richard


2020-01-06  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64-sve.md (@aarch64_sel_dup<mode>): Use Upl
	rather than Upa for CPY /M.

gcc/testsuite/
	* gcc.target/aarch64/sve/acle/general/cpy_1.c: New test.

Index: gcc/config/aarch64/aarch64-sve.md
===================================================================
--- gcc/config/aarch64/aarch64-sve.md	2020-01-06 12:58:16.453794569 +0000
+++ gcc/config/aarch64/aarch64-sve.md	2020-01-06 12:59:18.173388581 +0000
@@ -6523,7 +6523,7 @@ (define_insn "*vcond_mask_<mode><vpred>"
 (define_insn "@aarch64_sel_dup<mode>"
   [(set (match_operand:SVE_FULL 0 "register_operand" "=?w, w, ??w, ?&w, ??&w, ?&w")
 	(unspec:SVE_FULL
-	  [(match_operand:<VPRED> 3 "register_operand" "Upa, Upa, Upl, Upl, Upl, Upl")
+	  [(match_operand:<VPRED> 3 "register_operand" "Upl, Upl, Upl, Upl, Upl, Upl")
 	   (vec_duplicate:SVE_FULL
 	     (match_operand:<VEL> 1 "register_operand" "r, w, r, w, r, w"))
 	   (match_operand:SVE_FULL 2 "aarch64_simd_reg_or_zero" "0, 0, Dz, Dz, w, w")]
Index: gcc/testsuite/gcc.target/aarch64/sve/acle/general/cpy_1.c
===================================================================
--- /dev/null	2019-09-17 11:41:18.176664108 +0100
+++ gcc/testsuite/gcc.target/aarch64/sve/acle/general/cpy_1.c	2020-01-06 12:59:18.173388581 +0000
@@ -0,0 +1,42 @@
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include <arm_sve.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+** dup_x0_m:
+**	add	(x[0-9]+), x0, #?1
+**	mov	(p[0-7])\.b, p15\.b
+**	mov	z0\.d, \2/m, \1
+**	ret
+*/
+svuint64_t
+dup_x0_m (svuint64_t z0, uint64_t x0)
+{
+  register svbool_t pg asm ("p15");
+  asm volatile ("" : "=Upa" (pg));
+  return svdup_u64_m (z0, pg, x0 + 1);
+}
+
+/*
+** dup_d1_z:
+**	mov	(p[0-7])\.b, p15\.b
+**	mov	z0\.d, \1/m, d1
+**	ret
+*/
+svfloat64_t
+dup_d1_z (svfloat64_t z0, float64_t d1)
+{
+  register svbool_t pg asm ("p15");
+  asm volatile ("" : "=Upa" (pg));
+  return svdup_f64_m (z0, pg, d1);
+}
+
+#ifdef __cplusplus
+}
+#endif