[PATCH][AARCH64] Fix for PR86901

[Modi Mo via gcc-patches]

> > Sounds good. I'll get those setup and running and will report back on
> > findings. What's the preferred way to measure codesize? I'm assuming
> > by default the code pages are aligned so smaller differences would need to trip
> over the boundary to actually show up.
> 
> You can use the size command on the binaries:
> 
> >size /bin/ls
>    text	   data	    bss	    dec	    hex	filename
>  107271	   2024	   3472	 112767	  1b87f	/bin/ls
> 
> As you can see it shows the text size in bytes. It is not rounded up to a page, so it
> is an accurate measure of the codesize. Generally -O2 size is most useful to
> check (since that is what most applications build with), but -Ofast -flto can be
> useful as well (the global inlining means you get instruction combinations which
> appear less often with -O2).
> 
> Cheers,
> Wilco
Alrighty, I've got spec 2017 and spec 2006 setup and building. Using default configurations so -O2 in spec2006 and -O3 in spec2017. Testing the patch as last sent showed a 1% code size regression in spec 2017 perlbench which turned out to be a missing pattern for tbnz and all its variants:

(define_insn "*tb<optab><mode>1"
  [(set (pc) (if_then_else
	      (EQL (zero_extract:DI (match_operand:GPI 0 "register_operand" "r")  <--- only matches against zero_extract:DI
				    (const_int 1)
				    (match_operand 1
				      "aarch64_simd_shift_imm_<mode>" "n"))

The zero extract now matching against other modes would generate a test + branch rather than the combined instruction which led to the code size regression. I've updated the patch so that tbnz etc. matches GPI and that brings code size down to <0.2% in spec2017 and <0.4% in spec2006.

Spec results are attached for reference.

@Wilco I've gotten instruction on my side to set up an individual contributor's license for the time being. Can you send me the necessary documents to make that happen? Thanks!

ChangeLog:
2020-02-21  Di Mo  <modimo@microsoft.com>

gcc/
	* config/aarch64/aarch64.md: Add GPI modes to extsv/extv patterns. Allow tb<optab><mode>1 pattern to match against zero_extract:GPI.
	* expmed.c (extract_bit_field_using_extv): Change gen_lowpart to gen_lowpart_if_possible to avoid compiler assert building libgcc.
testsuite/
	* gcc.target/aarch64/pr86901.c: Add new test.

Modi
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