[PATCH], PR target/93569, Fix PowerPC vsx-builtin-15d.c test case

[Michael Meissner]

When I applied my previous patches for vec_extract, I switched to using
reg_to_non_prefixed to validate the vector extract address.  It uncovered a bug
that reg_to_non_prefixed allowed D-FORM (reg+offset) addresses to load up
Altivec registers on power7 and power8.  However, those systems only supported
X-FORM (reg+reg) addressing.  Power9 added support for DS-FORM and DQ-FORM
addressing to the Altivec registers.  This patch fixes this so that the
vsx-builtin-15d.c test case now passes.

Can I check this into the master branch?

I have done bootstrap builds and make check on both a little endian Power8
system and a big endian Power8 system.  There were no regressions.  On the big
endian system, just vsx-builtin-15d.c now passes.  On the little endian system,
vsx-builtin-15d.c now passes along with some Fortran tests.

2020-02-05  Michael Meissner  <meissner@linux.ibm.com>

	PR target/93569
	* config/rs6000/rs6000.c (reg_to_non_prefixed): Before ISA 3.0
	we only had X-FORM (reg+reg) addressing in the traditional Altivec
	registers.

--- /tmp/eAu61F_rs6000.c	2020-02-05 18:08:48.698992017 -0500
+++ gcc/config/rs6000/rs6000.c	2020-02-05 17:23:55.733650185 -0500
@@ -24943,9 +24943,13 @@ reg_to_non_prefixed (rtx reg, machine_mo
     }
 
   /* Altivec registers use DS-mode for scalars, and DQ-mode for vectors, IEEE
-     128-bit floating point, and 128-bit integers.  */
+     128-bit floating point, and 128-bit integers.  Before power9, only indexed
+     addressing was available.  */
   else if (ALTIVEC_REGNO_P (r))
     {
+      if (!TARGET_P9_VECTOR)
+	return NON_PREFIXED_X;
+
       if (mode == SFmode || size == 8 || FLOAT128_2REG_P (mode))
 	return NON_PREFIXED_DS;
 

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797