[PATCH, rs6000] Don't set MMA prefixed instruction length to 8

[Pat Haugen]

Fix instruction length for MMA insns.


Prefixed instructions should not have their length explicitly set to '8'. The function get_attr_length() will adjust the length appropriately based on the value of the "prefixed" attribute.

Bootstrap/regtest on powerpc64le (Power8/Power10) with no new regressions. Ok for trunk?

-Pat


2020-12-14  Pat Haugen  <pthaugen@linux.ibm.com>

gcc/
	* config/rs6000/mma.md (*movxo, mma_<vvi4i4i8>, mma_<avvi4i4i8>,
	mma_<vvi4i4i2>, mma_<avvi4i4i2>, mma_<vvi4i4>, mma_<avvi4i4>,
	mma_<pvi4i2>, mma_<apvi4i2>, mma_<vvi4i4i4>, mma_<avvi4i4i4>):
	Remove explicit setting of length attribute.
-------------- next part --------------
diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index 4d291c42f7a..ef4394416b6 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -318,7 +318,7 @@ (define_insn_and_split "*movxo"
   DONE;
 }
   [(set_attr "type" "vecload,vecstore,veclogical")
-   (set_attr "length" "8,8,16")
+   (set_attr "length" "*,*,16")
    (set_attr "max_prefixed_insns" "2,2,*")])
 
 (define_expand "mma_assemble_pair"
@@ -539,8 +539,7 @@ (define_insn "mma_<vvi4i4i8>"
 		    MMA_VVI4I4I8))]
   "TARGET_MMA"
   "<vvi4i4i8> %A0,%x1,%x2,%3,%4,%5"
-  [(set_attr "type" "mma")
-   (set_attr "length" "8")])
+  [(set_attr "type" "mma")])
 
 (define_insn "mma_<avvi4i4i8>"
   [(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
@@ -553,8 +552,7 @@ (define_insn "mma_<avvi4i4i8>"
 		    MMA_AVVI4I4I8))]
   "TARGET_MMA"
   "<avvi4i4i8> %A0,%x2,%x3,%4,%5,%6"
-  [(set_attr "type" "mma")
-   (set_attr "length" "8")])
+  [(set_attr "type" "mma")])
 
 (define_insn "mma_<vvi4i4i2>"
   [(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
@@ -566,8 +564,7 @@ (define_insn "mma_<vvi4i4i2>"
 		    MMA_VVI4I4I2))]
   "TARGET_MMA"
   "<vvi4i4i2> %A0,%x1,%x2,%3,%4,%5"
-  [(set_attr "type" "mma")
-   (set_attr "length" "8")])
+  [(set_attr "type" "mma")])
 
 (define_insn "mma_<avvi4i4i2>"
   [(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
@@ -580,8 +577,7 @@ (define_insn "mma_<avvi4i4i2>"
 		    MMA_AVVI4I4I2))]
   "TARGET_MMA"
   "<avvi4i4i2> %A0,%x2,%x3,%4,%5,%6"
-  [(set_attr "type" "mma")
-   (set_attr "length" "8")])
+  [(set_attr "type" "mma")])
 
 (define_insn "mma_<vvi4i4>"
   [(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
@@ -592,8 +588,7 @@ (define_insn "mma_<vvi4i4>"
 		    MMA_VVI4I4))]
   "TARGET_MMA"
   "<vvi4i4> %A0,%x1,%x2,%3,%4"
-  [(set_attr "type" "mma")
-   (set_attr "length" "8")])
+  [(set_attr "type" "mma")])
 
 (define_insn "mma_<avvi4i4>"
   [(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
@@ -605,8 +600,7 @@ (define_insn "mma_<avvi4i4>"
 		    MMA_AVVI4I4))]
   "TARGET_MMA"
   "<avvi4i4> %A0,%x2,%x3,%4,%5"
-  [(set_attr "type" "mma")
-   (set_attr "length" "8")])
+  [(set_attr "type" "mma")])
 
 (define_insn "mma_<pvi4i2>"
   [(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
@@ -617,8 +611,7 @@ (define_insn "mma_<pvi4i2>"
 		    MMA_PVI4I2))]
   "TARGET_MMA"
   "<pvi4i2> %A0,%x1,%x2,%3,%4"
-  [(set_attr "type" "mma")
-   (set_attr "length" "8")])
+  [(set_attr "type" "mma")])
 
 (define_insn "mma_<apvi4i2>"
   [(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
@@ -630,8 +623,7 @@ (define_insn "mma_<apvi4i2>"
 		    MMA_APVI4I2))]
   "TARGET_MMA"
   "<apvi4i2> %A0,%x2,%x3,%4,%5"
-  [(set_attr "type" "mma")
-   (set_attr "length" "8")])
+  [(set_attr "type" "mma")])
 
 (define_insn "mma_<vvi4i4i4>"
   [(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
@@ -643,8 +635,7 @@ (define_insn "mma_<vvi4i4i4>"
 		    MMA_VVI4I4I4))]
   "TARGET_MMA"
   "<vvi4i4i4> %A0,%x1,%x2,%3,%4,%5"
-  [(set_attr "type" "mma")
-   (set_attr "length" "8")])
+  [(set_attr "type" "mma")])
 
 (define_insn "mma_<avvi4i4i4>"
   [(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
@@ -657,5 +648,4 @@ (define_insn "mma_<avvi4i4i4>"
 		    MMA_AVVI4I4I4))]
   "TARGET_MMA"
   "<avvi4i4i4> %A0,%x2,%x3,%4,%5,%6"
-  [(set_attr "type" "mma")
-   (set_attr "length" "8")])
+  [(set_attr "type" "mma")])