[PATCH v3 3/4] arm: Auto-vectorization for MVE: vmvn
Kyrylo Tkachov
Kyrylo.Tkachov@arm.com
Mon Dec 14 09:54:00 GMT 2020
> -----Original Message-----
> From: Gcc-patches <gcc-patches-bounces@gcc.gnu.org> On Behalf Of
> Christophe Lyon via Gcc-patches
> Sent: 11 December 2020 18:37
> To: gcc-patches@gcc.gnu.org
> Subject: [PATCH v3 3/4] arm: Auto-vectorization for MVE: vmvn
>
> This patch enables MVE vmvnq instructions for auto-vectorization. MVE
> vmvnq insns in mve.md are modified to use 'not' instead of unspec
> expression to support one_cmpl<mode>2. The one_cmpl<mode>2 expander
> is added to vec-common.md.
Ok.
Thanks,
Kyrill
>
> 2020-12-11 Christophe Lyon <christophe.lyon@linaro.org>
>
> gcc/
> * config/arm/iterators.md (VDQNOTM2): New mode iterator.
> (supf): Remove VMVNQ_S and VMVNQ_U.
> (VMVNQ): Remove.
> * config/arm/mve.md (mve_vmvnq_u<mode>): New entry for vmvn
> instruction using expression not.
> (mve_vmvnq_s<mode>): New expander.
> * config/arm/neon.md (one_cmpl<mode>2): Renamed into
> one_cmpl<mode>2_neon.
> * config/arm/unspecs.md (VMVNQ_S, VMVNQ_U): Remove.
> * config/arm/vec-common.md (one_cmpl<mode>2): New expander.
>
> gcc/testsuite/
> * gcc.target/arm/simd/mve-vmvn.c: Add tests for vmvn.
> ---
> gcc/config/arm/iterators.md | 3 +--
> gcc/config/arm/mve.md | 14 +++++++----
> gcc/config/arm/neon.md | 4 ++--
> gcc/config/arm/unspecs.md | 2 --
> gcc/config/arm/vec-common.md | 6 +++++
> gcc/testsuite/gcc.target/arm/simd/mve-vmvn.c | 35
> ++++++++++++++++++++++++++++
> 6 files changed, 54 insertions(+), 10 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vmvn.c
>
> diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
> index 26351e0..036a939 100644
> --- a/gcc/config/arm/iterators.md
> +++ b/gcc/config/arm/iterators.md
> @@ -1216,7 +1216,7 @@ (define_int_attr mmla_sfx [(UNSPEC_MATMUL_S
> "s8") (UNSPEC_MATMUL_U "u8")
> (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u")
> (VREV16Q_S "s")
> (VREV16Q_U "u") (VMVNQ_N_S "s") (VMVNQ_N_U "u")
> (VCVTAQ_U "u") (VCVTAQ_S "s") (VREV64Q_S "s")
> - (VREV64Q_U "u") (VMVNQ_S "s") (VMVNQ_U "u")
> + (VREV64Q_U "u")
> (VDUPQ_N_U "u") (VDUPQ_N_S"s") (VADDVQ_S "s")
> (VADDVQ_U "u") (VADDVQ_S "s") (VADDVQ_U "u")
> (VMOVLTQ_U "u") (VMOVLTQ_S "s") (VMOVLBQ_S "s")
> @@ -1476,7 +1476,6 @@ (define_int_iterator VREV64Q [VREV64Q_S
> VREV64Q_U])
> (define_int_iterator VCVTQ_FROM_F [VCVTQ_FROM_F_S
> VCVTQ_FROM_F_U])
> (define_int_iterator VREV16Q [VREV16Q_U VREV16Q_S])
> (define_int_iterator VCVTAQ [VCVTAQ_U VCVTAQ_S])
> -(define_int_iterator VMVNQ [VMVNQ_U VMVNQ_S])
> (define_int_iterator VDUPQ_N [VDUPQ_N_U VDUPQ_N_S])
> (define_int_iterator VCLZQ [VCLZQ_U VCLZQ_S])
> (define_int_iterator VADDVQ [VADDVQ_U VADDVQ_S])
> diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
> index 0505537..86d7fc6 100644
> --- a/gcc/config/arm/mve.md
> +++ b/gcc/config/arm/mve.md
> @@ -433,16 +433,22 @@ (define_insn "mve_vnegq_s<mode>"
> ;;
> ;; [vmvnq_u, vmvnq_s])
> ;;
> -(define_insn "mve_vmvnq_<supf><mode>"
> +(define_insn "mve_vmvnq_u<mode>"
> [
> (set (match_operand:MVE_2 0 "s_register_operand" "=w")
> - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand"
> "w")]
> - VMVNQ))
> + (not:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")))
> ]
> "TARGET_HAVE_MVE"
> - "vmvn %q0, %q1"
> + "vmvn\t%q0, %q1"
> [(set_attr "type" "mve_move")
> ])
> +(define_expand "mve_vmvnq_s<mode>"
> + [
> + (set (match_operand:MVE_2 0 "s_register_operand")
> + (not:MVE_2 (match_operand:MVE_2 1 "s_register_operand")))
> + ]
> + "TARGET_HAVE_MVE"
> +)
>
> ;;
> ;; [vdupq_n_u, vdupq_n_s])
> diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
> index e1263b0..f58d4f5 100644
> --- a/gcc/config/arm/neon.md
> +++ b/gcc/config/arm/neon.md
> @@ -756,7 +756,7 @@ (define_insn "xor<mode>3_neon"
> [(set_attr "type" "neon_logic<q>")]
> )
>
> -(define_insn "one_cmpl<mode>2"
> +(define_insn "one_cmpl<mode>2_neon"
> [(set (match_operand:VDQ 0 "s_register_operand" "=w")
> (not:VDQ (match_operand:VDQ 1 "s_register_operand" "w")))]
> "TARGET_NEON"
> @@ -3240,7 +3240,7 @@ (define_expand "neon_vmvn<mode>"
> (match_operand:VDQIW 1 "s_register_operand")]
> "TARGET_NEON"
> {
> - emit_insn (gen_one_cmpl<mode>2 (operands[0], operands[1]));
> + emit_insn (gen_one_cmpl<mode>2_neon (operands[0], operands[1]));
> DONE;
> })
>
> diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md
> index 8a4389a..e581645 100644
> --- a/gcc/config/arm/unspecs.md
> +++ b/gcc/config/arm/unspecs.md
> @@ -550,8 +550,6 @@ (define_c_enum "unspec" [
> VREV64Q_U
> VQABSQ_S
> VNEGQ_S
> - VMVNQ_S
> - VMVNQ_U
> VDUPQ_N_U
> VDUPQ_N_S
> VCLZQ_U
> diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-
> common.md
> index 030ed82..37ff518 100644
> --- a/gcc/config/arm/vec-common.md
> +++ b/gcc/config/arm/vec-common.md
> @@ -193,3 +193,9 @@ (define_expand "xor<mode>3"
> (match_operand:VDQ 2 "s_register_operand" "")))]
> "ARM_HAVE_<MODE>_ARITH"
> )
> +
> +(define_expand "one_cmpl<mode>2"
> + [(set (match_operand:VDQ 0 "s_register_operand")
> + (not:VDQ (match_operand:VDQ 1 "s_register_operand")))]
> + "ARM_HAVE_<MODE>_ARITH"
> +)
> diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vmvn.c
> b/gcc/testsuite/gcc.target/arm/simd/mve-vmvn.c
> new file mode 100644
> index 0000000..73e897a
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vmvn.c
> @@ -0,0 +1,35 @@
> +/* { dg-do assemble } */
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O3" } */
> +
> +#include <stdint.h>
> +
> +#define FUNC(SIGN, TYPE, BITS, NB, OP, NAME)
> \
> + void test_ ## NAME ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t *
> __restrict__ dest, TYPE##BITS##_t *a) { \
> + int i; \
> + for (i=0; i<NB; i++) { \
> + dest[i] = OP a[i]; \
> + } \
> +}
> +
> +/* vmnvq supports only 16-bit and 32-bit elements. */
> +/* 64-bit vectors. */
> +FUNC(s, int, 32, 2, ~, vmvn)
> +FUNC(u, uint, 32, 2, ~, vmvn)
> +FUNC(s, int, 16, 4, ~, vmvn)
> +FUNC(u, uint, 16, 4, ~, vmvn)
> +FUNC(s, int, 8, 8, ~, vmvn)
> +FUNC(u, uint, 8, 8, ~, vmvn)
> +
> +/* 128-bit vectors. */
> +FUNC(s, int, 32, 4, ~, vmvn)
> +FUNC(u, uint, 32, 4, ~, vmvn)
> +FUNC(s, int, 16, 8, ~, vmvn)
> +FUNC(u, uint, 16, 8, ~, vmvn)
> +FUNC(s, int, 8, 16, ~, vmvn)
> +FUNC(u, uint, 8, 16, ~, vmvn)
> +
> +/* MVE has only 128-bit vectors, so we can vectorize only half of the
> + functions above. */
> +/* { dg-final { scan-assembler-times {vmvn\tq[0-9]+, q[0-9]+} 6 } } */
> --
> 2.7.4
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