[PATCH] [Refactor] [AVX512] Combine VI12_AVX512VL with VI48_AVX512VL into VI_AVX512VLBW

[Hongtao Liu]

Hi:
There're many pairs of define_insn/define_expand that are very similar
to each other except mode iterator and condition. For these patterns
VI12_AVX512VL are used under condition TARGET_AVX512BW, and
VI48_AVX512VL are used under condition TARGET_AVX512F.

This patch is about to introduce a new iterator VI_AVX512VLBW to
combine a pair of those patterns into one.

There are no functional changes, just code refactoring.

Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?

gcc/ChangeLog

        * config/i386/sse.md (VI_AVX512VLBW): New mode iterator.
        (<avx512>_ucmp<mode>3<mask_scalar_merge_name>): Combine
        two patterns with mode iterator VI12_AVX512VL and VI48_AVX512VL
        into one pattern with mode iterator VI_AVX512VLBW.
        (vec_cmpu<mode><avx512fmaskmodelower>): Ditto.
        (<avx512>_cvt<ssemodesuffix>2mask<mode>): Ditto.
        (<avx512>_cvtmask2<ssemodesuffix><mode>): Ditto.
        (*<avx512>_cvtmask2<ssemodesuffix><mode>): Ditto.
        (<plusminus_insn><mode>3_mask): Ditto.
        (*<plusminus_insn><mode>3_mask): Ditto.
        (<avx512>_eq<mode>3<mask_scalar_merge_name>): Ditto.
        (<avx512>_eq<mode>3<mask_scalar_merge_name>_1): Ditto.
        (<avx512>_gt<mode>3<mask_scalar_merge_name>): Ditto.
        (<sse2_avx2>_andnot<mode>3_mask): Ditto.
        (abs<mode>2_mask): Ditto.
        (*<avx512>_<code><mode>3<mask_name>): Combine from ...
        (*avx512f_<code><mode>3<mask_name>)
        and (<mask_codefor><code><mode>3<mask_name>).


-- 
BR,
Hongtao
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