[PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.

Carl Love cel@us.ibm.com
Thu Aug 27 15:43:40 GMT 2020


GCC maintainers:

The following patch has been updated based on the comments from Will
and Segher.  

The patch is a subset of the mainline commit:

   commit
   07d456bb80a16405723c98c2ab74ccc2a5a23898                            
        
   Author: Carl Love <carll@us.ibm.com>                                
               
   Date:   Mon Aug 10 19:37:41 2020
   -0500                                          
                                                                       
               
       rs6000, restrict bfloat convert intrinsic to Power 10. Fix
   BU_P10V macro definitions.

Only the changes from the mainline patch to restrict the bfloat convert
intrinsics (XVCVBF16SPN and XVCVSPBF16) to Power 10 are included in
this patch.  This patch adds the BU_P10V_VSX_1 macro definition for
Power 10.  The macro definition restricts the use of the named
intrinsics similarly to Power 8 and Power 9.

The changes for the BU_10V macro definitions from the mainline patch do
not apply to the GCC 10 branch as the macro definitions and uses do not
exist in the GCC 10 branch.  

The patch has been updated per the comments above.  It was rebased onto
the latest GCC 10 code base and retested on 

  powerpc64le-unknown-linux-gnu (Power 9 LE)

with no regressions.  Please let me know if this patch is acceptable
for the GCC 10 branch.  Thank you.

                 Carl Love

--------------------------------------------------------------------
rs6000, restrict bfloat convert intrinsic to Power 10.

gcc/ChangeLog

2020-08-26  Carl Love  <cel@us.ibm.com>
	* config/rs6000/rs6000-builtin.def: (BU_P10V_VSX_1) New builtin macro expansion.
	(XVCVBF16SPN, XVCVSPBF16): Replace macro expansion BU_VSX_1 with BU_P10V_VSX_1.
	* config/rs6000/rs6000-call.c: (VSX_BUILTIN_XVCVSPBF16, VSX_BUILTIN_XVCVBF16SPN):
	Replace with P10V_BUILTIN_XVCVSPBF16, P10V_BUILTIN_XVCVBF16SPN respectively.
---
 gcc/config/rs6000/rs6000-builtin.def | 12 ++++++++++--
 gcc/config/rs6000/rs6000-call.c      |  4 ++--
 2 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def
index 88f78cb0a15..5de17e79855 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -1014,6 +1014,14 @@
 		     | RS6000_BTC_BINARY),				\
 		    CODE_FOR_ ## ICODE)			/* ICODE */
 
+/* Built-ins for ISA 3.1 Altivec instructions.  */
+#define BU_P10V_VSX_1(ENUM, NAME, ATTR, ICODE)\
+  RS6000_BUILTIN_1 (P10V_BUILTIN_ ## ENUM,		/* ENUM */      \
+		    "__builtin_vsx_" NAME,		/* NAME */      \
+		    RS6000_BTM_P10,			/* MASK */      \
+		    (RS6000_BTC_ ## ATTR		/* ATTR */      \
+		    | RS6000_BTC_UNARY),				\
+		    CODE_FOR_ ## ICODE)			/* ICODE */
 #endif
 
 

@@ -2698,8 +2706,8 @@ BU_SPECIAL_X (RS6000_BUILTIN_CFSTRING, "__builtin_cfstring", RS6000_BTM_ALWAYS,
 	      RS6000_BTC_MISC)
 
 /* POWER10 MMA builtins.  */
-BU_VSX_1 (XVCVBF16SPN,	    "xvcvbf16spn",	MISC, vsx_xvcvbf16spn)
-BU_VSX_1 (XVCVSPBF16,	    "xvcvspbf16",	MISC, vsx_xvcvspbf16)
+BU_P10V_VSX_1 (XVCVBF16SPN,	    "xvcvbf16spn",	MISC, vsx_xvcvbf16spn)
+BU_P10V_VSX_1 (XVCVSPBF16,	    "xvcvspbf16",	MISC, vsx_xvcvspbf16)
 
 BU_MMA_1 (XXMFACC,	    "xxmfacc",		QUAD, mma_xxmfacc)
 BU_MMA_1 (XXMTACC,	    "xxmtacc",		QUAD, mma_xxmtacc)
diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c
index 2cf78dfa5fe..fc1671e1bb2 100644
--- a/gcc/config/rs6000/rs6000-call.c
+++ b/gcc/config/rs6000/rs6000-call.c
@@ -13383,8 +13383,8 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
     case P8V_BUILTIN_VGBBD:
     case MISC_BUILTIN_CDTBCD:
     case MISC_BUILTIN_CBCDTD:
-    case VSX_BUILTIN_XVCVSPBF16:
-    case VSX_BUILTIN_XVCVBF16SPN:
+    case P10V_BUILTIN_XVCVSPBF16:
+    case P10V_BUILTIN_XVCVBF16SPN:
       h.uns_p[0] = 1;
       h.uns_p[1] = 1;
       break;
-- 
2.17.1




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