[PATCH] cmpelim: recognize extra clobbers in insns

Richard Sandiford richard.sandiford@arm.com
Wed Aug 19 11:05:28 GMT 2020


Sorry for the slow reply.

Pip Cet via Gcc-patches <gcc-patches@gcc.gnu.org> writes:
> I'm working on the AVR cc0 -> CCmode conversion (bug#92729). One
> problem is that the cmpelim pass is currently very strict in requiring
> insns of the form
>
> (parallel [(set (reg:SI) (op:SI ... ...))
>            (clobber (reg:CC REG_CC))])
>
> when in fact AVR's insns often have the form
>
> (parallel [(set (reg:SI) (op:SI ... ...))
>            (clobber (scratch:QI))
>            (clobber (reg:CC REG_CC))])
>
> The attached patch relaxes checks in the cmpelim code to recognize
> such insns, and makes it attempt to recognize
>
> (parallel [(set (reg:CC REG_CC) (compare:CC ... ...))
>            (set (reg:SI (op:SI ... ...)))
>        (clobber (scratch:QI))])
>
> as a new insn for that example. This appears to work.

The idea looks good.  However, I think it'd be better (or at least
more usual) for the define_insns to list the clobbers the other
way around:

(parallel [(set (reg:SI) (op:SI ... ...))
           (clobber (reg:CC REG_CC))
           (clobber (scratch:QI))])

(clobber (scratch…))s generally come last because any rtl optimisation
pass that uses recog can automatically add any necessary
(clobber (scratch…))s.  In contrast, very few passes (probably just
combine) know how to add (clobber (reg:CC REG_CC)) to a pattern that
didn't already have it.  This is because adding a REG_CC clobber
requires the pass to “prove” that REG_CC is dead at that point,
whereas there are no restrictions on adding a scratch clobber.

Thanks,
Richard


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