[PATCH 1/4][PR target/88808]Enable bitwise operator for AVX512 masks.

Uros Bizjak ubizjak@gmail.com
Mon Aug 17 09:20:14 GMT 2020


On Fri, Aug 14, 2020 at 10:22 AM Hongtao Liu <crazylht@gmail.com> wrote:
>
> Hi:
>   First, since avx512 masks involve both vector isa and general part,
> so i add both maintainers to the maillist.
>
>   I'm doing this in 4 steps:
>   1 - Add cost model for operation of mask registers.
>   2 - Introduce new cover class INT_MASK_REGS, this will enable direct
> move between gpr and mask registers in pass_reload by consideration of
> cost model, this is similar as INT_SSE_REGS.
>   3 - Tune cost model.
>   4 - Enable operator or/xor/and/andn/not for mask register. kxnor is
> not enabled since there's no corresponding instruction for general
> registers, 64bit mask op is not enabled for 32bit target.
> kadd/kshift/ktest are not merged into general versionsadd/ashl/test
> since i think it would be odd to use mask register for those
> operations.
>
>   Bootstrap is ok, regression test is ok for i386/x86-64 result.
>   There's some improvement for performance of SPEC2017 tested on SKL,
> i observe there're many spills from integer to mask registers instead
> of memory which is the reason for the improvement.

+  if (MASK_CLASS_P (regclass))
+    {
+      int index;
+      switch (GET_MODE_SIZE (mode))
+    {
+    case 1:
+      index = 0;
+      break;
+    case 2:
+      index = 1;
+      break;
+    default:
+      index = 3;

Max index = 2!

+      break;
+    }
+
+      if (in == 2)
+    return MAX (ix86_cost->hard_register.mask_load[index],
+            ix86_cost->hard_register.mask_store[index]);
+      return in ? ix86_cost->hard_register.mask_load[2]
+    : ix86_cost->hard_register.mask_store[2];
+    }

Are DImode loads and stores assumed to cost the same as SImode? A
comment would be nice here.

Uros.


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