[PATCH 1/4][PR target/88808]Enable bitwise operator for AVX512 masks.

Hongtao Liu crazylht@gmail.com
Fri Aug 14 08:23:08 GMT 2020


Hi:
  First, since avx512 masks involve both vector isa and general part,
so i add both maintainers to the maillist.

  I'm doing this in 4 steps:
  1 - Add cost model for operation of mask registers.
  2 - Introduce new cover class INT_MASK_REGS, this will enable direct
move between gpr and mask registers in pass_reload by consideration of
cost model, this is similar as INT_SSE_REGS.
  3 - Tune cost model.
  4 - Enable operator or/xor/and/andn/not for mask register. kxnor is
not enabled since there's no corresponding instruction for general
registers, 64bit mask op is not enabled for 32bit target.
kadd/kshift/ktest are not merged into general versionsadd/ashl/test
since i think it would be odd to use mask register for those
operations.

  Bootstrap is ok, regression test is ok for i386/x86-64 result.
  There's some improvement for performance of SPEC2017 tested on SKL,
i observe there're many spills from integer to mask registers instead
of memory which is the reason for the improvement.

500.perlbench_r 0.65%
502.gcc_r 0.32%
505.mcf_r -0.75%
520.omnetpp_r 2.15%
523.xalancbmk_r -0.95%
525.x264_r 1.83%
531.deepsjeng_r 0.00%
541.leela_r 0.66%
548.exchange2_r -0.45%
557.xz_r -0.94%
INT geomean 0.25%
503.bwaves_r 0.00%
507.cactuBSSN_r 0.78%
508.namd_r 0.34%
510.parest_r 0.16%
511.povray_r 1.37%
519.lbm_r 1.33%
521.wrf_r 0.04%
526.blender_r 0.15%
527.cam4_r 0.69%
538.imagick_r 0.51%
544.nab_r 0.27%
549.fotonik3d_r 2.00%
554.roms_r 4.35%
FP geomean 0.99%


-- 
BR,
Hongtao
-------------- next part --------------
A non-text attachment was scrubbed...
Name: 0001-x86-Add-cost-model-for-operation-of-mask-registers.patch
Type: text/x-patch
Size: 17157 bytes
Desc: not available
URL: <https://gcc.gnu.org/pipermail/gcc-patches/attachments/20200814/06e2ef72/attachment-0001.bin>


More information about the Gcc-patches mailing list