[PATCH 1/4][PR target/88808]Enable bitwise operator for AVX512 masks.
Fri Aug 14 08:23:08 GMT 2020
First, since avx512 masks involve both vector isa and general part,
so i add both maintainers to the maillist.
I'm doing this in 4 steps:
1 - Add cost model for operation of mask registers.
2 - Introduce new cover class INT_MASK_REGS, this will enable direct
move between gpr and mask registers in pass_reload by consideration of
cost model, this is similar as INT_SSE_REGS.
3 - Tune cost model.
4 - Enable operator or/xor/and/andn/not for mask register. kxnor is
not enabled since there's no corresponding instruction for general
registers, 64bit mask op is not enabled for 32bit target.
kadd/kshift/ktest are not merged into general versionsadd/ashl/test
since i think it would be odd to use mask register for those
Bootstrap is ok, regression test is ok for i386/x86-64 result.
There's some improvement for performance of SPEC2017 tested on SKL,
i observe there're many spills from integer to mask registers instead
of memory which is the reason for the improvement.
INT geomean 0.25%
FP geomean 0.99%
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