[PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.

Carl Love cel@us.ibm.com
Thu Aug 13 19:24:54 GMT 2020


Bill:

On Thu, 2020-08-13 at 13:38 -0500, Bill Schmidt wrote:
> Hi Carl,
> 
> Thanks for cleaning up the consistency issue.  The new names and
> related 
> adjustments LGTM.
> 
> Are there no affected test cases that need adjusting?  That
> surprises 
> me.  For example, didn't __builtin_altivec_xxeval become 
> __builtin_vsx_xxeval as a result of this change?  Does that not
> appear 
> in any test cases?
> 
> Thanks,
> 
> Bill

In gcc/config/rs6000/rs6000-builtin.def we have

#define vec_ternarylogic(a, b, c, d)   __builtin_vec_xxeval (a, b, c, d)

The vec_ternarylogic() builtin is used in test files 
gcc/testsuite/gcc.target/powerpc/vec-ternarylogic-X.c where X stands
for 1, 2, 3, 4, 5, 6, 7, 8, 9.

In gcc/confit/rs6000/rs6000-builtin.def 

BU_P10V_VSX_4 (XXEVAL, "xxeval", CONST, xxeval) 

now expands to __builtin_vsx_xxeval as you expect.

I do not  see a test case that uses the old builtin name
__builtin_altivec_xxeval.

carll@genoa:~/GCC/gcc-mainline-935/gcc/testsuite/gcc.target/powerpc$
grep -r  xxeval *
vec-ternarylogic-0.c:/* { dg-final { scan-assembler {\mxxeval\M} } } */
vec-ternarylogic-2.c:/* { dg-final { scan-assembler {\mxxeval\M} } } */
vec-ternarylogic-3.c:/* { dg-final { scan-assembler {\mxxeval\M} } } */
vec-ternarylogic-4.c:/* { dg-final { scan-assembler {\mxxeval\M} } } */
vec-ternarylogic-6.c:/* { dg-final { scan-assembler {\mxxeval\M} } } */
vec-ternarylogic-8.c:/* { dg-final { scan-assembler {\mxxeval\M} } } */
vec-ternarylogic-9.c:/* { dg-final { scan-assembler {\mxxeval\M} } } */
carll@genoa:~/GCC/gcc-mainline-935/gcc/testsuite/gcc.target/powerpc$ 

There just seems to be the various tests that are expected to generate
the xxeval instruction.  As far as I can see there is no test program that uses the __builtin_altivec_xxeval name. 

                     Carl 



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