[PATCH] aarch64: Add A64FX machine model

[Richard Sandiford]

Qian Jianhua <qianjh@cn.fujitsu.com> writes:
> This patch add support for Fujitsu A64FX, as the first step of adding
> A64FX machine model.
>
> A64FX is used in FUJITSU Supercomputer PRIMEHPC FX1000,
> PRIMEHPC FX700, and supercomputer Fugaku.
> The official microarchitecture information of A64FX can be read at
> https://github.com/fujitsu/A64FX.
>
> Changelog:
> 2020-08-03 Qian jianhua <qianjh@cn.fujitsu.com>
>
> 	* config/aarch64/aarch64-cores.def: Add the chip name.
> 	* config/aarch64/aarch64-tune.md: Regenerated.
> 	* config/aarch64/aarch64.c: Add tuning table for the chip.
> 	* doc/invoke.texi: Add the new name to the list.
> 					
> Test results:
> * Bootstrap on aarch64 ------------------------------- [OK]
> * Regression tests ----------------------------------- [OK]
> * Compile with -mcpu=a64fx --------------------------- [OK]

Thanks for doing this, looks great.  Pushed to trunk and the GCC 10 branch.

Would you like the patch to be backported further than GCC 10?  I wasn't
sure whether GCC 9 and earlier would be useful, given that those releases
didn't support the ACLE and were missing optimisations that went into GCC 10.

Very minor, but I tweaked the changelog entry slightly to:

2020-08-03  Qian jianhua  <qianjh@cn.fujitsu.com>

gcc/
	* config/aarch64/aarch64-cores.def (a64fx): New core.
	* config/aarch64/aarch64-tune.md: Regenerated.
	* config/aarch64/aarch64.c (a64fx_prefetch_tune, a64fx_tunings): New.
	* doc/invoke.texi: Add a64fx to the list.

before committing.  The changelog entries are automatically applied to files
like gcc/ChangeLog on a nightly basis, and doing that would lose the context
in the covering message about which chip the patch is supporting.

Does the attached patch to document the addition to GCC 10.3 look OK?
We'll need something similar for GCC 11, but personally I tend to prefer
adding the notes closer to the release.

Thanks,
Richard

-------------- next part --------------
>From 671bc9f0c545040b2c2a255b68f461d9f26aa302 Mon Sep 17 00:00:00 2001
From: Richard Sandiford <richard.sandiford@arm.com>
Date: Mon, 3 Aug 2020 12:34:31 +0100
Subject: [PATCH] Document A64FX support in GCC 10.3

---
 htdocs/gcc-10/changes.html | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/htdocs/gcc-10/changes.html b/htdocs/gcc-10/changes.html
index b40f9a57..be396747 100644
--- a/htdocs/gcc-10/changes.html
+++ b/htdocs/gcc-10/changes.html
@@ -1093,6 +1093,24 @@ known to be fixed in the 10.2 release. This list might not be
 complete (that is, it is possible that some PRs that have been fixed
 are not listed here).</p>
 
+<!-- .................................................................. -->
+<h2 id="GCC10.3">GCC 10.3</h2>
+
+<h3>Target Specific Changes</h3>
+
+<h4>AArch64</h4>
+<ul>
+  <li>GCC now supports the Fujitsu A64FX.  The associated <code>-mcpu</code>
+  and <code>-mtune</code> options are <code>-mcpu=a64fx</code> and
+  <code>-mtune=a64fx</code> respectively.  In particular,
+  <code>-mcpu=a64fx</code> generates code for Armv8.2-A with SVE and tunes
+  the code for the A64FX.  This tuning includes optimizing SVE code
+  for a 512-bit vector length, although by default the code is still
+  length-agnostic and so works for all SVE implementations.
+  Adding <code>-msve-vector-bits=512</code> makes the code specific
+  to 512-bit SVE.</li>
+</ul>
+
 <!-- .................................................................. -->
 
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