Problem exposed by recent ARM multiply changes

Richard Earnshaw (lists) Richard.Earnshaw@arm.com
Fri Sep 27 15:17:00 GMT 2019


On 26/09/2019 07:49, Jakub Jelinek wrote:
> On Wed, Sep 25, 2019 at 10:06:13PM -0600, Jeff Law wrote:
>> (insn 13 12 14 2 (set (reg:SI 124)
>>          (const_int -939524096 [0xffffffffc8000000])) "j.c":10:54 161
>> {*arm_movsi_insn}
>>       (nil))
>>
>> (insn 14 13 16 2 (parallel [
>>              (set (reg:SI 132)
>>                  (plus:SI (mult:SI (zero_extend:DI (reg/v:SI 115 [ sec ]))
>>                          (zero_extend:DI (reg:SI 124)))
>>                      (reg:SI 130)))
> 
> IMNSHO the bug is just in the backend, the above is not valid RTL.
> SImode MULT has to have SImode operands, not DImode operands.
> 
>>              (set (reg:SI 133 [+4 ])
>>                  (plus:SI (truncate:SI (lshiftrt:DI (plus:DI (mult:DI
>> (zero_extend:DI (reg/v:SI 115 [ sec ]))
>>                                      (zero_extend:DI (reg:SI 124)))
>>                                  (zero_extend:DI (reg:SI 130)))
>>                              (const_int 32 [0x20])))
>>                      (reg:SI 131 [+4 ])))
> 
>  From the rest of the pattern, I'd say the right fix is just to:
> --- gcc/config/arm/arm.md.jj	2019-09-20 23:17:28.786629241 +0200
> +++ gcc/config/arm/arm.md	2019-09-26 08:47:40.068517793 +0200
> @@ -1812,8 +1812,8 @@
>     [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
>   	(plus:SI
>   	 (mult:SI
> -	  (SE:DI (match_operand:SI 4 "s_register_operand" "%r,r"))
> -	  (SE:DI (match_operand:SI 5 "s_register_operand" "r,r")))
> +	  (match_operand:SI 4 "s_register_operand" "%r,r")
> +	  (match_operand:SI 5 "s_register_operand" "r,r"))
>   	 (match_operand:SI 1 "s_register_operand" "0,0")))
>      (set (match_operand:SI 2 "s_register_operand" "=r,&r")
>   	(plus:SI
> because it really only cares about the DImode zext values in the second part
> of the instruction, but I don't have spare cycles to test this right now nor
> write testcases.
> 
> 	Jakub
> 

Yes, this looks like a simple cut-and-paste error.  This patch is approved.

R.



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