[PATCH][ARM] Remove support for MULS
Richard Earnshaw (lists)
Richard.Earnshaw@arm.com
Thu Sep 19 09:52:00 GMT 2019
On 18/09/2019 17:31, Kyrill Tkachov wrote:
> Hi Wilco,
>
> On 9/9/19 6:07 PM, Wilco Dijkstra wrote:
>> ping
>>
>>
>> Remove various MULS/MLAS patterns which are enabled when optimizing for
>>  size. However the codesize gain from these patterns is so minimal that
>> Â there is no point in keeping them.
>>
> I disagree. If they still trigger and generate better code than without
> we should keep them.
>
> What kind of code is *common* varies greatly from user to user.
Also, the main reason for restricting their use was that in the 'olden
days', when we had multi-cycle implementations of the multiply
instructions with short-circuit fast termination when the result was
completed, the flag setting variants would never short-circuit.
These days we have fixed cycle counts for multiply instructions, so this
is no-longer a penalty. In the thumb2 case in particular we can often
reduce mul-cmp (6 bytes) to muls (2 bytes), that's a 66% saving on this
sequence and definitely worth exploiting when we can, even if it's not
all that common.
In fact, give the latest architectural implementations, I think we
should look again at re-enabling these when doing normal optimization as
well.
R.
>
> Thanks,
>
> Kyrill
>
>
>> Â Bootstrap OK on armhf, regress passes.
>>
>> Â ChangeLog:
>>  2019-09-03 Wilco Dijkstra <wdijkstr@arm.com>
>>
>> Â Â Â Â Â Â Â Â * config/arm/arm.md (mulsi3_compare0): Remove pattern.
>> Â Â Â Â Â Â Â Â (mulsi3_compare0_v6): Likewise.
>> Â Â Â Â Â Â Â Â (mulsi_compare0_scratch): Likewise.
>> Â Â Â Â Â Â Â Â (mulsi_compare0_scratch_v6): Likewise.
>> Â Â Â Â Â Â Â Â (mulsi3addsi_compare0): Likewise.
>> Â Â Â Â Â Â Â Â (mulsi3addsi_compare0_v6): Likewise.
>> Â Â Â Â Â Â Â Â (mulsi3addsi_compare0_scratch): Likewise.
>> Â Â Â Â Â Â Â Â (mulsi3addsi_compare0_scratch_v6): Likewise.
>> Â Â Â Â Â Â Â Â * config/arm/thumb2.md (thumb2_mulsi_short_compare0): Remove
>> pattern.
>> Â Â Â Â Â Â Â Â (thumb2_mulsi_short_compare0_scratch): Likewise.
>>
>> Â --
>> Â diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
>> Â index
>> 738d42fd164f117f1dec1108a824d984ccd70d09..66dafdc47b7cfc37c131764e482d47bcaab90538
>> 100644
>> Â --- a/gcc/config/arm/arm.md
>> Â +++ b/gcc/config/arm/arm.md
>> Â @@ -1618,60 +1618,6 @@ (define_insn "*arm_mulsi3_v6"
>> Â Â Â Â (set_attr "predicable_short_it" "yes,yes,no")]
>> Â )
>>
>> Â -(define_insn "*mulsi3_compare0"
>> Â -Â [(set (reg:CC_NOOV CC_REGNUM)
>> Â -Â Â Â Â Â Â (compare:CC_NOOV (mult:SI
>> Â -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (match_operand:SI 2 "s_register_operand"
>> "r,r")
>> Â -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (match_operand:SI 1 "s_register_operand"
>> "%0,r"))
>> Â -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (const_int 0)))
>> Â -Â Â (set (match_operand:SI 0 "s_register_operand" "=&r,&r")
>> Â -Â Â Â Â Â Â (mult:SI (match_dup 2) (match_dup 1)))]
>> Â -Â "TARGET_ARM && !arm_arch6"
>> Â -Â "muls%?\\t%0, %2, %1"
>> Â -Â [(set_attr "conds" "set")
>> Â -Â Â (set_attr "type" "muls")]
>> Â -)
>> Â -
>> Â -(define_insn "*mulsi3_compare0_v6"
>> Â -Â [(set (reg:CC_NOOV CC_REGNUM)
>> Â -Â Â Â Â Â Â (compare:CC_NOOV (mult:SI
>> Â -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (match_operand:SI 2 "s_register_operand" "r")
>> Â -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (match_operand:SI 1 "s_register_operand" "r"))
>> Â -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (const_int 0)))
>> Â -Â Â (set (match_operand:SI 0 "s_register_operand" "=r")
>> Â -Â Â Â Â Â Â (mult:SI (match_dup 2) (match_dup 1)))]
>> Â -Â "TARGET_ARM && arm_arch6 && optimize_size"
>> Â -Â "muls%?\\t%0, %2, %1"
>> Â -Â [(set_attr "conds" "set")
>> Â -Â Â (set_attr "type" "muls")]
>> Â -)
>> Â -
>> Â -(define_insn "*mulsi_compare0_scratch"
>> Â -Â [(set (reg:CC_NOOV CC_REGNUM)
>> Â -Â Â Â Â Â Â (compare:CC_NOOV (mult:SI
>> Â -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (match_operand:SI 2 "s_register_operand"
>> "r,r")
>> Â -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (match_operand:SI 1 "s_register_operand"
>> "%0,r"))
>> Â -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (const_int 0)))
>> Â -Â Â (clobber (match_scratch:SI 0 "=&r,&r"))]
>> Â -Â "TARGET_ARM && !arm_arch6"
>> Â -Â "muls%?\\t%0, %2, %1"
>> Â -Â [(set_attr "conds" "set")
>> Â -Â Â (set_attr "type" "muls")]
>> Â -)
>> Â -
>> Â -(define_insn "*mulsi_compare0_scratch_v6"
>> Â -Â [(set (reg:CC_NOOV CC_REGNUM)
>> Â -Â Â Â Â Â Â (compare:CC_NOOV (mult:SI
>> Â -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (match_operand:SI 2 "s_register_operand" "r")
>> Â -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (match_operand:SI 1 "s_register_operand" "r"))
>> Â -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (const_int 0)))
>> Â -Â Â (clobber (match_scratch:SI 0 "=r"))]
>> Â -Â "TARGET_ARM && arm_arch6 && optimize_size"
>> Â -Â "muls%?\\t%0, %2, %1"
>> Â -Â [(set_attr "conds" "set")
>> Â -Â Â (set_attr "type" "muls")]
>> Â -)
>> Â -
>> Â ;; Unnamed templates to match MLA instruction.
>>
>> Â (define_insn "*mulsi3addsi"
>> Â @@ -1698,70 +1644,6 @@ (define_insn "*mulsi3addsi_v6"
>> Â Â Â Â (set_attr "predicable" "yes")]
>> Â )
>>
>> Â -(define_insn "*mulsi3addsi_compare0"
>> Â -Â [(set (reg:CC_NOOV CC_REGNUM)
>> Â -Â Â Â Â Â Â (compare:CC_NOOV
>> Â -Â Â Â Â Â Â Â (plus:SI (mult:SI
>> Â -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (match_operand:SI 2 "s_register_operand" "r,r,r,r")
>> Â -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (match_operand:SI 1 "s_register_operand" "%0,r,0,r"))
>> Â -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (match_operand:SI 3 "s_register_operand" "r,r,0,0"))
>> Â -Â Â Â Â Â Â Â (const_int 0)))
>> Â -Â Â (set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r,&r")
>> Â -Â Â Â Â Â Â (plus:SI (mult:SI (match_dup 2) (match_dup 1))
>> Â -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (match_dup 3)))]
>> Â -Â "TARGET_ARM && arm_arch6"
>> Â -Â "mlas%?\\t%0, %2, %1, %3"
>> Â -Â [(set_attr "conds" "set")
>> Â -Â Â (set_attr "type" "mlas")]
>> Â -)
>> Â -
>> Â -(define_insn "*mulsi3addsi_compare0_v6"
>> Â -Â [(set (reg:CC_NOOV CC_REGNUM)
>> Â -Â Â Â Â Â Â (compare:CC_NOOV
>> Â -Â Â Â Â Â Â Â (plus:SI (mult:SI
>> Â -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (match_operand:SI 2 "s_register_operand" "r")
>> Â -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (match_operand:SI 1 "s_register_operand" "r"))
>> Â -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (match_operand:SI 3 "s_register_operand" "r"))
>> Â -Â Â Â Â Â Â Â (const_int 0)))
>> Â -Â Â (set (match_operand:SI 0 "s_register_operand" "=r")
>> Â -Â Â Â Â Â Â (plus:SI (mult:SI (match_dup 2) (match_dup 1))
>> Â -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (match_dup 3)))]
>> Â -Â "TARGET_ARM && arm_arch6 && optimize_size"
>> Â -Â "mlas%?\\t%0, %2, %1, %3"
>> Â -Â [(set_attr "conds" "set")
>> Â -Â Â (set_attr "type" "mlas")]
>> Â -)
>> Â -
>> Â -(define_insn "*mulsi3addsi_compare0_scratch"
>> Â -Â [(set (reg:CC_NOOV CC_REGNUM)
>> Â -Â Â Â Â Â Â (compare:CC_NOOV
>> Â -Â Â Â Â Â Â Â (plus:SI (mult:SI
>> Â -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (match_operand:SI 2 "s_register_operand" "r,r,r,r")
>> Â -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (match_operand:SI 1 "s_register_operand" "%0,r,0,r"))
>> Â -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (match_operand:SI 3 "s_register_operand" "?r,r,0,0"))
>> Â -Â Â Â Â Â Â Â (const_int 0)))
>> Â -Â Â (clobber (match_scratch:SI 0 "=&r,&r,&r,&r"))]
>> Â -Â "TARGET_ARM && !arm_arch6"
>> Â -Â "mlas%?\\t%0, %2, %1, %3"
>> Â -Â [(set_attr "conds" "set")
>> Â -Â Â (set_attr "type" "mlas")]
>> Â -)
>> Â -
>> Â -(define_insn "*mulsi3addsi_compare0_scratch_v6"
>> Â -Â [(set (reg:CC_NOOV CC_REGNUM)
>> Â -Â Â Â Â Â Â (compare:CC_NOOV
>> Â -Â Â Â Â Â Â Â (plus:SI (mult:SI
>> Â -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (match_operand:SI 2 "s_register_operand" "r")
>> Â -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (match_operand:SI 1 "s_register_operand" "r"))
>> Â -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (match_operand:SI 3 "s_register_operand" "r"))
>> Â -Â Â Â Â Â Â Â (const_int 0)))
>> Â -Â Â (clobber (match_scratch:SI 0 "=r"))]
>> Â -Â "TARGET_ARM && arm_arch6 && optimize_size"
>> Â -Â "mlas%?\\t%0, %2, %1, %3"
>> Â -Â [(set_attr "conds" "set")
>> Â -Â Â (set_attr "type" "mlas")]
>> Â -)
>> Â -
>> Â (define_insn "*mulsi3subsi"
>> Â Â Â [(set (match_operand:SI 0 "s_register_operand" "=r")
>> Â Â Â Â Â Â Â Â Â (minus:SI
>> Â diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md
>> Â index
>> 6ccc875e2b4e7b8ce256e52da966dfe220c6f5d6..8e26689b66263e7304a0da6163ceccfb4483d3e7
>> 100644
>> Â --- a/gcc/config/arm/thumb2.md
>> Â +++ b/gcc/config/arm/thumb2.md
>> Â @@ -1381,31 +1381,6 @@ (define_insn "*thumb2_mulsi_short"
>> Â Â Â Â (set_attr "length" "2")
>> Â Â Â Â (set_attr "type" "muls")])
>>
>> Â -(define_insn "*thumb2_mulsi_short_compare0"
>> Â -Â [(set (reg:CC_NOOV CC_REGNUM)
>> Â -Â Â Â Â Â Â Â (compare:CC_NOOV
>> Â -Â Â Â Â Â Â Â Â (mult:SI (match_operand:SI 1 "register_operand" "%0")
>> Â -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (match_operand:SI 2 "register_operand" "l"))
>> Â -Â Â Â Â Â Â Â Â (const_int 0)))
>> Â -Â Â (set (match_operand:SI 0 "register_operand" "=l")
>> Â -Â Â Â Â Â Â (mult:SI (match_dup 1) (match_dup 2)))]
>> Â -Â "TARGET_THUMB2 && optimize_size"
>> Â -Â "muls\\t%0, %2, %0"
>> Â -Â [(set_attr "length" "2")
>> Â -Â Â (set_attr "type" "muls")])
>> Â -
>> Â -(define_insn "*thumb2_mulsi_short_compare0_scratch"
>> Â -Â [(set (reg:CC_NOOV CC_REGNUM)
>> Â -Â Â Â Â Â Â Â (compare:CC_NOOV
>> Â -Â Â Â Â Â Â Â Â (mult:SI (match_operand:SI 1 "register_operand" "%0")
>> Â -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (match_operand:SI 2 "register_operand" "l"))
>> Â -Â Â Â Â Â Â Â Â (const_int 0)))
>> Â -Â Â (clobber (match_scratch:SI 0 "=l"))]
>> Â -Â "TARGET_THUMB2 && optimize_size"
>> Â -Â "muls\\t%0, %2, %0"
>> Â -Â [(set_attr "length" "2")
>> Â -Â Â (set_attr "type" "muls")])
>> Â -
>> Â (define_insn "*thumb2_cbz"
>> Â Â Â [(set (pc) (if_then_else
>> Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (eq (match_operand:SI 0 "s_register_operand" "l,?r")
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