[PATCH] [MIPS] Replace insert with insve for floating-point values

[Mihailo Stojanovic]

Currently, when a function argument of type double gets loaded into a
vector register on a 32-bit target, it is firstly reloaded into two
general purpose registers, and then loaded into a vector register using
two insert.w instructions.

This patch swaps the two insert.w instructions with one insve.d
instruction, which operates on 64-bit floating point registers, so the
value can be reloaded into a FPR. This is done by adding another
alternative of constraints for msa_insert_<msafmt_f> pattern, which
covers the case of a floating-point input value.

gcc/ChangeLog:

        * config/mips/mips-msa.md (msa_insert_<msaftm_f>): Add an
        alternative which covers the floating-point input value. Also
        forbid the split of insert.d pattern for floating-point values.

gcc/testsuite/ChangeLog:

        * gcc.target/mips/msa-insert-split.c: New test.
---
 gcc/config/mips/mips-msa.md                      | 11 ++++++++---
 gcc/testsuite/gcc.target/mips/msa-insert-split.c | 16 ++++++++++++++++
 2 files changed, 24 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/mips/msa-insert-split.c

diff --git a/gcc/config/mips/mips-msa.md b/gcc/config/mips/mips-msa.md
index 929646d..628423d 100644
--- a/gcc/config/mips/mips-msa.md
+++ b/gcc/config/mips/mips-msa.md
@@ -436,14 +436,17 @@
 })
 
 (define_insn "msa_insert_<msafmt_f>"
-  [(set (match_operand:MSA 0 "register_operand" "=f")
+  [(set (match_operand:MSA 0 "register_operand" "=f,f")
 	(vec_merge:MSA
 	  (vec_duplicate:MSA
-	    (match_operand:<UNITMODE> 1 "reg_or_0_operand" "dJ"))
-	  (match_operand:MSA 2 "register_operand" "0")
+	    (match_operand:<UNITMODE> 1 "reg_or_0_operand" "dJ,f"))
+	  (match_operand:MSA 2 "register_operand" "0,0")
 	  (match_operand 3 "const_<bitmask>_operand" "")))]
   "ISA_HAS_MSA"
 {
+  if (which_alternative == 1)
+    return "insve.<msafmt>\t%w0[%y3],%w1[0]";
+
   if (!TARGET_64BIT && (<MODE>mode == V2DImode || <MODE>mode == V2DFmode))
     return "#";
   else
@@ -462,6 +465,8 @@
   "reload_completed && ISA_HAS_MSA && !TARGET_64BIT"
   [(const_int 0)]
 {
+  if (REG_P (operands[1]) && FP_REG_P (REGNO (operands[1])))
+    FAIL;
   mips_split_msa_insert_d (operands[0], operands[2], operands[3], operands[1]);
   DONE;
 })
diff --git a/gcc/testsuite/gcc.target/mips/msa-insert-split.c b/gcc/testsuite/gcc.target/mips/msa-insert-split.c
new file mode 100644
index 0000000..50f3b8a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/msa-insert-split.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-mfp64 -mhard-float -mmsa" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+typedef double v2f64 __attribute__ ((vector_size (16)));
+
+void foo (double* arr, v2f64* vec)
+{
+  v2f64 v;
+  v[0] = arr[0];
+  v[1] = arr[1];
+  *vec = v;
+}
+
+/* { dg-final { scan-assembler-not "insert.w" } } */
+/* { dg-final { scan-assembler-times "insve.d" 2 } } */
-- 
2.7.4