Restrict bb-slp-40.c to targets with VnQI addition (PR 92366)

[Richard Sandiford]

bb-slp-40.c fails on SPARC targets without VIS4 because it
requires addition on vectors of bytes.  There doesn't seem to be
an existing target selector for this, so I added vect_char_add.
(Wasn't sure whether to use vect_char_add, for consistency
with vect_no_int_add/vect_int_mult etc., or vect_add_char for
consistency with vect_shift_char etc.)

I took the target list from vect_int and removed targets that didn't
seem to support the operation (namely sparc*, since we don't seem to
have any test for VIS4, niagara7 or m8, and alpha*-*-*.)

Tested on aarch64-linux-gnu, x86_64-linux-gnu, powerpc64-linux-gnu
(Power 7) and sparc-sun-solaris2.11.  OK to install?

Richard


2019-11-20  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	PR testsuite/92366
	* doc/sourcebuild.texi (vect_char_add): Document.

gcc/testsuite/
	PR testsuite/92366
	* lib/target-supports.exp (check_effective_target_vect_char_add):
	New proc.
	* gcc.dg/vect/bb-slp-40.c: Require vect_char_add instead of vect_int.

Index: gcc/doc/sourcebuild.texi
===================================================================
--- gcc/doc/sourcebuild.texi	2019-11-18 15:36:04.865884928 +0000
+++ gcc/doc/sourcebuild.texi	2019-11-20 15:11:52.572010515 +0000
@@ -1522,6 +1522,10 @@ Target does not support a vector add ins
 @item vect_no_bitwise
 Target does not support vector bitwise instructions.
 
+@item vect_char_add
+Target supports addition of @code{char} vectors for at least one
+vector length.
+
 @item vect_char_mult
 Target supports @code{vector char} multiplication.
 
Index: gcc/testsuite/lib/target-supports.exp
===================================================================
--- gcc/testsuite/lib/target-supports.exp	2019-11-18 15:36:04.869884903 +0000
+++ gcc/testsuite/lib/target-supports.exp	2019-11-20 15:11:52.580010459 +0000
@@ -5749,6 +5749,27 @@ proc check_effective_target_vect_bswap {
 	     || [istarget amdgcn-*-*] }}]
 }
 
+# Return 1 if the target supports addition of char vectors for at least
+# one vector length.
+
+proc check_effective_target_vect_char_add { } {
+    return [check_cached_effective_target_indexed vect_int {
+      expr {
+         [istarget i?86-*-*] || [istarget x86_64-*-*]
+         || ([istarget powerpc*-*-*]
+	     && ![istarget powerpc-*-linux*paired*])
+	 || [istarget amdgcn-*-*]
+	 || [istarget ia64-*-*]
+	 || [istarget aarch64*-*-*]
+	 || [is-effective-target arm_neon]
+	 || ([istarget mips*-*-*]
+	     && ([et-is-effective-target mips_loongson_mmi]
+	     || [et-is-effective-target mips_msa]))
+	 || ([istarget s390*-*-*]
+	     && [check_effective_target_s390_vx])
+	}}]
+}
+
 # Return 1 if the target supports hardware vector shift operation for char.
 
 proc check_effective_target_vect_shift_char { } {
Index: gcc/testsuite/gcc.dg/vect/bb-slp-40.c
===================================================================
--- gcc/testsuite/gcc.dg/vect/bb-slp-40.c	2019-11-19 16:25:49.000000000 +0000
+++ gcc/testsuite/gcc.dg/vect/bb-slp-40.c	2019-11-20 15:11:52.572010515 +0000
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* { dg-additional-options "-fvect-cost-model=dynamic" } */
-/* { dg-require-effective-target vect_int } */
+/* { dg-require-effective-target vect_char_add } */
 
 char g_d[1024], g_s1[1024], g_s2[1024];
 void foo(void)