[PATCH 1/4] Preliminary m68k patches
Bernd Schmidt
bernds_cb1@t-online.de
Wed Nov 13 13:09:00 GMT 2019
This tidies up a few spots in the m68k backend in preparation for the
large patch to follow. This is purely for review purposes: this patch
has not been tested independently, and will be committed together with
the following one.
Noteworthy changes:
Some patterns and peepholes were unified through mode iterators. The
m68k_subword_comparison_operator predicate was adapted to also work with
SImode.
There are already scc_di patterns, so there is no need to generate a cc0
set/use pair in cstoredi.
Without HAVE_cc0, combine sometimes substitutes a stack push into the
destination of a divmod instruction, and then gets confused because it
doesn't seem to expect it in a PARALLEL. Since the instruction only
works on registers anyway, use register_operand.
There are patterns that use register_operand with "do" constraints which
allow memory. This works at reload time, but the instruction can not be
rerecognized later on. This becomes a problem if such operands occur in
a jump instruction, as subsequent passes will try to redirect branches
and thus attempt to rerecognize the pattern.
movqi/movhi do not accept constants that are not CONST_INT. The code to
output them would not set flags correctly and was changed to
gcc_unreachable.
Comments were added to some patterns which are not being generated due
to incorrect tests/predicates. Fixing these is out of scope for this
work, but the problems are at least documented.
All the passes working on conditional traps seem to assume
const_true_rtx is used for unconditional ones, rather than const1_rtx.
Bernd
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