[PATCH][AArch64] PR tree-optimization/90332: Implement vec_init<M><N> where N is a vector mode

[Kyrill Tkachov]

Ping.

https://gcc.gnu.org/ml/gcc-patches/2019-05/msg00477.html

Thanks,

Kyrill

On 5/10/19 10:32 AM, Kyrill Tkachov wrote:
> Hi all,
>
> This patch fixes the failing gcc.dg/vect/slp-reduc-sad-2.c testcase on 
> aarch64
> by implementing a vec_init optab that can handle two half-width 
> vectors producing a full-width one
> by concatenating them.
>
> In the gcc.dg/vect/slp-reduc-sad-2.c case it's a V8QI reg concatenated 
> with a V8QI const_vector of zeroes.
> This can be implemented efficiently using the aarch64_combinez pattern 
> that just loads a D-register to make
> use of the implicit zero-extending semantics of that load.
> Otherwise it concatenates the two vector using aarch64_simd_combine.
>
> With this patch I'm seeing the effect from richi's original patch that 
> added gcc.dg/vect/slp-reduc-sad-2.c on aarch64
> and 525.x264_r improves by about 1.5%.
>
> Bootstrapped and tested on aarch64-none-linux-gnu. Also tested on 
> aarch64_be-none-elf.
>
> Ok for trunk?
> Thanks,
> Kyrill
>
> 2019-10-05  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
>
> Â Â Â  PR tree-optimization/90332
> Â Â Â  * config/aarch64/aarch64.c (aarch64_expand_vector_init):
> Â Â Â  Handle VALS containing two vectors.
> Â Â Â  * config/aarch64/aarch64-simd.md (*aarch64_combinez<mode>): Rename
> Â Â Â  to...
> Â Â Â  (@aarch64_combinez<mode>): ... This.
> Â Â Â  (*aarch64_combinez_be<mode>): Rename to...
> Â Â Â  (@aarch64_combinez_be<mode>): ... This.
> Â Â Â  (vec_init<mode><Vhalf>): New define_expand.
> Â Â Â  * config/aarch64/iterators.md (Vhalf): Handle V8HF.
>