[PATCH, i386]: Introduce signbit<mode>2 expander
Uros Bizjak
ubizjak@gmail.com
Tue May 21 16:01:00 GMT 2019
Based on the recent work that enabled vectorization of
__builtin_signbit on aarch64.
2019-05-21 Uroš Bizjak <ubizjak@gmail.com>
* config/i386/sse.md (VF1_AVX2): New mode iterator.
(signbit<mode>2): New expander
testsuite/ChangeLog:
2019-05-21 Uroš Bizjak <ubizjak@gmail.com>
* gcc.target/i386/vect-signbitf.c: New test.
Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Committed to mainline SVN.
Uros.
-------------- next part --------------
Index: config/i386/sse.md
===================================================================
--- config/i386/sse.md (revision 271467)
+++ config/i386/sse.md (working copy)
@@ -279,6 +279,9 @@
(define_mode_iterator VF1
[(V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX") V4SF])
+(define_mode_iterator VF1_AVX2
+ [(V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX2") V4SF])
+
;; 128- and 256-bit SF vector modes
(define_mode_iterator VF1_128_256
[(V8SF "TARGET_AVX") V4SF])
@@ -3523,6 +3526,15 @@
operands[4] = gen_reg_rtx (<MODE>mode);
})
+(define_expand "signbit<mode>2"
+ [(set (match_operand:<sseintvecmode> 0 "register_operand")
+ (lshiftrt:<sseintvecmode>
+ (subreg:<sseintvecmode>
+ (match_operand:VF1_AVX2 1 "register_operand") 0)
+ (match_dup 2)))]
+ "TARGET_SSE2"
+ "operands[2] = GEN_INT (GET_MODE_UNIT_BITSIZE (<MODE>mode)-1);")
+
;; Also define scalar versions. These are used for abs, neg, and
;; conditional move. Using subregs into vector modes causes register
;; allocation lossage. These patterns do not allow memory operands
Index: testsuite/gcc.target/i386/vect-signbitf.c
===================================================================
--- testsuite/gcc.target/i386/vect-signbitf.c (nonexistent)
+++ testsuite/gcc.target/i386/vect-signbitf.c (working copy)
@@ -0,0 +1,30 @@
+/* { dg-do run { target sse2_runtime } } */
+/* { dg-options "-O2 -msse2 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */
+
+extern void abort ();
+
+#define N 1024
+float a[N] = {0.0f, -0.0f, 1.0f, -1.0f,
+ -2.0f, 3.0f, -5.0f, -8.0f,
+ 13.0f, 21.0f, -25.0f, 33.0f};
+int r[N];
+
+int
+main (void)
+{
+ int i;
+
+ for (i = 0; i < N; i++)
+ r[i] = __builtin_signbitf (a[i]);
+
+ /* check results: */
+ for (i = 0; i < N; i++)
+ if (__builtin_signbit (a[i]) && !r[i])
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
+/* { dg-final { scan-assembler-not "-2147483648" } } */
+/* { dg-final { scan-assembler "psrld" } } */
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