[PATCH] libphobos: RISC-V: Fix soft-float build errors with IEEE exception flags

[Maciej W. Rozycki]

On Thu, 2 May 2019, Jim Wilson wrote:

> > within inline assembly, to access IEEE exception flags.  The use of
> > these instructions is not allowed when building for a soft-float ABI.
> 
> Technically it is an architecture issue not an ABI issue.  If you
> compile for -march=rv32imac -mabi=ilp32 then you can't use FP
> instructions.  If you compile for -march=rv32imafc -mabi=ilp32 then
> you can use FP instructions, but we don't use FP regs for argument
> passing.  This is similar to the distinction that ARM makes between
> the soft and softfp ABIs.  The RISC-V newlib port for instance checks
> __riscv_flen to decide whether to use FP instructions.  The predefined
> macro __riscv_flen is set to 0 if the target architecture doesn't have
> FP registers.  So the choice of using FP instructions depends on the
> target architecture, not the target ABI.

 I found this a useful clarification, thank you!  I wasn't aware of the 
`-march=rv32imafc -mabi=ilp32' hybrid mode.

> This is how it works in the C front end.  We have __riscv_flen which
> can be 0, 4, or 8 and which indicates the hardware FP register size in
> bytes.  And we have __riscv_float_abi_soft, __riscv_float_abi_single,
> and __riscv_float_abi_double, only one of which is defined, which
> indicates the max size of arguments that can be passed in FP
> registers.

 FWIW it makes sense to me, and I find the nomenclature somewhat clearer 
than ARM's `soft' vs `softfp' modes, though I think one still has to refer 
to documentation to understand the distinction between these variants.

  Maciej