[PATCH] x86: fix/improve vgf2p8affine*qb insns

Jan Beulich JBeulich@suse.com
Thu Jun 27 11:39:00 GMT 2019


>>> On 27.06.19 at 12:58, <ubizjak@gmail.com> wrote:
> On Thu, Jun 27, 2019 at 12:49 PM Jan Beulich <JBeulich@suse.com> wrote:
>>
>> >>> On 27.06.19 at 12:20, <ubizjak@gmail.com> wrote:
>> > On Thu, Jun 27, 2019 at 10:57 AM Jan Beulich <JBeulich@suse.com> wrote:
>> >>
>> >> - the affine transformations are not commutative (the two source
>> >>   operands have entirely different meaning)
>> >> - there's no need for three alternatives
>> >> - the nonimmediate_operand/Bm combination can better be vector_operand/m
>> >>
>> >> gcc/
>> >> 2019-06-27  Jan Beulich  <jbeulich@suse.com>
>> >>
>> >>         * config/i386/sse.md (vgf2p8affineinvqb_<mode><mask_name>,
>> >>         vgf2p8affineqb_<mode><mask_name>): Drop % constraint modifier.
>> >>         Eliminate redundant alternative.  Use vector_operand plus "m"
>> >>         constraint.
>> >
>> > Please just drop % modifier and use vector_operand here. IIRC,
>> > register allocator operates on constraints, it doesn't care for
>> > predicates. But predicates shouldn't be more constrained than
>> > constraints. So, having "m" instead of "Bm" is a bad idea with
>> > vector_operand.
>>
>> Well, putting back the Bm is easy (if that's really needed). But do
>> you also mean me to put back to redundant 3rd alternative?
> 
> It is not redundant, "x" and "v" are different register constraints.

Well, yes, "v" is covering a wider set than "x". But only if AVX512F
is enabled. The original combinations ("x", "avx") and ("v", "avx512f")
are thus effectively the same as the new ("v", "avx"). But yes - I
guess I'll split this from the actual bug fix.

Jan




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