[patch][aarch64]: add usra and ssra combine patterns

[Sylvia Taylor]

Updating patch with missing scan-assembler checks.

Cheers,
Syl

-----Original Message-----
From: Sylvia Taylor 
Sent: 04 June 2019 12:24
To: James Greenhalgh <james.greenhalgh@arm.com>
Cc: Richard Earnshaw <Richard.Earnshaw@arm.com>; Marcus Shawcroft <Marcus.Shawcroft@arm.com>; gcc-patches@gcc.gnu.org; nd <nd@arm.com>
Subject: RE: [patch][aarch64]: add usra and ssra combine patterns

Hi James,

I've managed to remove the odd redundant git diff change.

Regarding aarch64_<sur>sra_n<mode>, this patch shouldn't affect it.

I am also not aware of any way of enabling this combine inside the pattern used for those intrinsics, so I kept them separate.

Cheers,
Syl

-----Original Message-----
From: James Greenhalgh <james.greenhalgh@arm.com>
Sent: 03 June 2019 11:20
To: Sylvia Taylor <Sylvia.Taylor@arm.com>
Cc: Richard Earnshaw <Richard.Earnshaw@arm.com>; Marcus Shawcroft <Marcus.Shawcroft@arm.com>; gcc-patches@gcc.gnu.org; nd <nd@arm.com>
Subject: Re: [patch][aarch64]: add usra and ssra combine patterns

On Thu, May 30, 2019 at 03:25:19PM +0100, Sylvia Taylor wrote:
> Greetings,
> 
> This patch adds support to combine:
> 
> 1) ushr and add into usra, example:
> 
> ushr	v0.16b, v0.16b, 2
> add	v0.16b, v0.16b, v2.16b
> ---
> usra	v2.16b, v0.16b, 2
> 
> 2) sshr and add into ssra, example:
> 
> sshr	v1.16b, v1.16b, 2
> add	v1.16b, v1.16b, v3.16b
> ---
> ssra	v3.16b, v1.16b, 2
> 
> Bootstrapped and tested on aarch64-none-linux-gnu.
> 
> Ok for trunk? If yes, I don't have any commit rights, so can someone 
> please commit it on my behalf.

This patch has an unrelated change to
aarch64_get_lane_zero_extend<GPI:mode><VDQQH:mode> Please revert that and resend.

What changes (if any) should we make to aarch64_<sur>sra_n<mode> based on this patch, and to the vsra_n intrinsics in arm_neon.h ?

Thanks,
James

> 
> Cheers,
> Syl
> 
> gcc/ChangeLog:
> 
> 2019-05-30  Sylvia Taylor  <sylvia.taylor@arm.com>
> 
> 	* config/aarch64/aarch64-simd.md
> 	(*aarch64_simd_sra<mode>): New.
> 	* config/aarch64/iterators.md
> 	(SHIFTRT): New iterator.
> 	(sra_op): New attribute.
> 
> gcc/testsuite/ChangeLog:
> 
> 2019-05-30  Sylvia Taylor  <sylvia.taylor@arm.com>
> 
> 	* gcc.target/aarch64/simd/ssra.c: New test.
> 	* gcc.target/aarch64/simd/usra.c: New test.

> diff --git a/gcc/config/aarch64/aarch64-simd.md
> b/gcc/config/aarch64/aarch64-simd.md
> index
> e3852c5d182b70978d7603225fce55c0b8ee2894..502ac5f3b45a1da059bb07701150
> a531091378ed 100644
> --- a/gcc/config/aarch64/aarch64-simd.md
> +++ b/gcc/config/aarch64/aarch64-simd.md
> @@ -3110,22 +3122,22 @@
>      operands[2] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[2]));
>      return "smov\\t%<GPI:w>0, %1.<VDQQH:Vetype>[%2]";
>    }
> -  [(set_attr "type" "neon_to_gp<q>")]
> -)
> -
> -(define_insn "*aarch64_get_lane_zero_extend<GPI:mode><VDQQH:mode>"
> -  [(set (match_operand:GPI 0 "register_operand" "=r")
> -	(zero_extend:GPI
> -	  (vec_select:<VEL>
> -	    (match_operand:VDQQH 1 "register_operand" "w")
> -	    (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))]
> -  "TARGET_SIMD"
> -  {
> -    operands[2] = aarch64_endian_lane_rtx (<VDQQH:MODE>mode,
> -					   INTVAL (operands[2]));
> -    return "umov\\t%w0, %1.<Vetype>[%2]";
> -  }
> -  [(set_attr "type" "neon_to_gp<q>")]
> +  [(set_attr "type" "neon_to_gp<q>")]
> +)
> +
> +(define_insn "*aarch64_get_lane_zero_extend<GPI:mode><VDQQH:mode>"
> +  [(set (match_operand:GPI 0 "register_operand" "=r")
> +	(zero_extend:GPI
> +	  (vec_select:<VEL>
> +	    (match_operand:VDQQH 1 "register_operand" "w")
> +	    (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))]
> +  "TARGET_SIMD"
> +  {
> +    operands[2] = aarch64_endian_lane_rtx (<VDQQH:MODE>mode,
> +					   INTVAL (operands[2]));
> +    return "umov\\t%w0, %1.<Vetype>[%2]";
> +  }
> +  [(set_attr "type" "neon_to_gp<q>")]
>  )
>  
>  ;; Lane extraction of a value, neither sign nor zero extension

These changes should be dropped.


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