[AArch64] [SVE] PR88837 - Poor vector construction code in VL-specific mode

[Richard Sandiford]

Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> writes:
>> > diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
>> > index 3bd6e815715..0ff0d8fb757 100644
>> > --- a/gcc/testsuite/lib/target-supports.exp
>> > +++ b/gcc/testsuite/lib/target-supports.exp
>> > @@ -3846,6 +3846,10 @@ proc add_options_for_arm_neon_softfp_fp16 { flags } {
>> >      return "$flags $et_arm_neon_softfp_fp16_flags"
>> >  }
>> >
>> > +proc add_options_for_arm_sve { flags } {
>> > +    return "$flags -march=armv8.2-a+sve"
>>
>> ...this I think we should avoid overriding the flags if they already
>> select SVE, so probably:
>>
>>     if { ![istarget aarch64*-*-*] || [check_effective_target_aarch64_sve] } {
>>         return "$flags"
>>     }
>>
>> Should be "aarch64_sve" rather than "arm_sve".
>>
>> > +}
>> > +
>> >  # Return 1 if this is an ARM target supporting the FP16 alternative
>> >  # format.  Some multilibs may be incompatible with the options needed.  Also
>> >  # set et_arm_neon_fp16_flags to the best options to add.
>> > @@ -4323,7 +4327,7 @@ proc check_effective_target_aarch64_sve_hw { } {
>> >         asm volatile ("ptrue p0.b");
>> >         return 0;
>> >       }
>> > -    }]
>> > +    } [ add_options_for_arm_sve "" ]]
>> >  }
>> >
>> >  # Return true if this is an AArch64 target that can run SVE code and
>> > @@ -4343,7 +4347,7 @@ proc aarch64_sve_hw_bits { bits } {
>> >           __builtin_abort ();
>> >         return 0;
>> >       }
>> > -    }]]
>> > +    }] [add_options_for_arm_sve ""] ]
>> >  }
>> >
>> >  # Return true if this is an AArch64 target that can run SVE code and
>>
>> Think the formatting in the second is preferred over the first (i.e.
>> no spaces inside the [...]).
> Does the attached patch look OK ?

Yes, thanks.  (With a suitable changelog of course :-))

Richard

>
> Thanks,
> Prathamesh
>>
>> Thanks,
>> Richard
>
> diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
> index 3bd6e815715..2b3e5d26004 100644
> --- a/gcc/testsuite/lib/target-supports.exp
> +++ b/gcc/testsuite/lib/target-supports.exp
> @@ -3846,6 +3846,13 @@ proc add_options_for_arm_neon_softfp_fp16 { flags } {
>      return "$flags $et_arm_neon_softfp_fp16_flags"
>  }
>  
> +proc add_options_for_aarch64_sve { flags } {
> +    if { ![istarget aarch64*-*-*] || [check_effective_target_aarch64_sve] } {
> +        return "$flags"
> +    }
> +    return "$flags -march=armv8.2-a+sve"
> +}
> +
>  # Return 1 if this is an ARM target supporting the FP16 alternative
>  # format.  Some multilibs may be incompatible with the options needed.  Also
>  # set et_arm_neon_fp16_flags to the best options to add.
> @@ -4323,7 +4330,7 @@ proc check_effective_target_aarch64_sve_hw { } {
>  	  asm volatile ("ptrue p0.b");
>  	  return 0;
>  	}
> -    }]
> +    } [add_options_for_aarch64_sve ""]]
>  }
>  
>  # Return true if this is an AArch64 target that can run SVE code and
> @@ -4343,7 +4350,7 @@ proc aarch64_sve_hw_bits { bits } {
>  	    __builtin_abort ();
>  	  return 0;
>  	}
> -    }]]
> +    }] [add_options_for_aarch64_sve ""]]
>  }
>  
>  # Return true if this is an AArch64 target that can run SVE code and