[PATCH 12/43] i386: Emulate MMX vec_dupv2si with SSE
H.J. Lu
hjl.tools@gmail.com
Sun Feb 10 21:01:00 GMT 2019
On Sun, Feb 10, 2019 at 2:36 AM Uros Bizjak <ubizjak@gmail.com> wrote:
>
> On 2/10/19, H.J. Lu <hjl.tools@gmail.com> wrote:
> > Emulate MMX vec_dupv2si with SSE. Only SSE register source operand is
> > allowed.
> >
> > PR target/89021
> > * config/i386/mmx.md (*vec_dupv2si): Changed to
> > define_insn_and_split and also allow TARGET_MMX_WITH_SSE to
> > support SSE emulation.
> > * config/i386/sse.md (*vec_dupv4si): Renamed to ...
> > (vec_dupv4si): This.
> > ---
> > gcc/config/i386/mmx.md | 27 ++++++++++++++++++++-------
> > gcc/config/i386/sse.md | 2 +-
> > 2 files changed, 21 insertions(+), 8 deletions(-)
> >
> > diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
> > index d360e97c98b..1ee51c5deb7 100644
> > --- a/gcc/config/i386/mmx.md
> > +++ b/gcc/config/i386/mmx.md
> > @@ -1420,14 +1420,27 @@
> > (set_attr "length_immediate" "1")
> > (set_attr "mode" "DI")])
> >
> > -(define_insn "*vec_dupv2si"
> > - [(set (match_operand:V2SI 0 "register_operand" "=y")
> > +(define_insn_and_split "*vec_dupv2si"
> > + [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv")
> > (vec_duplicate:V2SI
> > - (match_operand:SI 1 "register_operand" "0")))]
> > - "TARGET_MMX"
> > - "punpckldq\t%0, %0"
> > - [(set_attr "type" "mmxcvt")
> > - (set_attr "mode" "DI")])
> > + (match_operand:SI 1 "register_operand" "0,0,Yv")))]
> > + "TARGET_MMX || TARGET_MMX_WITH_SSE"
> > + "@
> > + punpckldq\t%0, %0
> > + #
> > + #"
> > + "&& reload_completed && TARGET_MMX_WITH_SSE"
>
> Please fix above.
I will use
"TARGET_MMX_WITH_SSE && reload_completed"
> > + [(const_int 0)]
> > +{
> > + /* Emulate MMX vec_dupv2si with SSE vec_dupv4si. */
> > + rtx op0 = gen_rtx_REG (V4SImode, REGNO (operands[0]));
> > + rtx insn = gen_vec_dupv4si (op0, operands[1]);
> > + emit_insn (insn);
> > + DONE;
>
> Please write this simple RTX explicitly in the place of (const_int 0) above.
rtx insn = gen_vec_dupv4si (op0, operands[1]);
is easy. How do I write
rtx op0 = gen_rtx_REG (V4SImode, REGNO (operands[0]));
in place of (const_int 0)?
> Uros.
>
> > +}
> > + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
> > + (set_attr "type" "mmxcvt,ssemov,ssemov")
> > + (set_attr "mode" "DI,TI,TI")])
> >
> > (define_insn "*mmx_concatv2si"
> > [(set (match_operand:V2SI 0 "register_operand" "=y,y")
> > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> > index 5dc0930ac1f..7d2c0367911 100644
> > --- a/gcc/config/i386/sse.md
> > +++ b/gcc/config/i386/sse.md
> > @@ -18976,7 +18976,7 @@
> > (set_attr "prefix" "maybe_evex,maybe_evex,orig")
> > (set_attr "mode" "V4SF")])
> >
> > -(define_insn "*vec_dupv4si"
> > +(define_insn "vec_dupv4si"
> > [(set (match_operand:V4SI 0 "register_operand" "=v,v,x")
> > (vec_duplicate:V4SI
> > (match_operand:SI 1 "nonimmediate_operand" "Yv,m,0")))]
> > --
> > 2.20.1
> >
> >
--
H.J.
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