[committed, amdgcn] Add sub-dword add/sub patterns

[Andrew Stubbs]

This patch add vector add and sub instruction patterns for V64QI and 
V64HI modes.

The instructions used are actually 32-bit as GCN does not support 
sub-dword operations in this way, but I believe it ought to be safe for 
these operations, provided that the excess bits are ignored properly 
elsewhere.

This results in 80 new test passes. There are a few regressions from 
vectorization tests that took a different code path and encountered 
another missing instruction.

Andrew
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