[PATCH, GCC/ARM, 2/2] Add support for ASRL(imm), LSLL(imm) and LSRL(imm) instructions for Armv8.1-M Mainline

Kyrill Tkachov kyrylo.tkachov@foss.arm.com
Wed Dec 11 17:54:00 GMT 2019 

Hi Mihail,

On 11/14/19 1:54 PM, Mihail Ionescu wrote:
> Hi,
>
> This is part of a series of patches where I am trying to add new
> instructions for Armv8.1-M Mainline to the arm backend.
> This patch is adding the following instructions:
>
> ASRL (imm)
> LSLL (imm)
> LSRL (imm)
>
>
> ChangeLog entry are as follow:
>
> *** gcc/ChangeLog ***
>
> 2019-11-14  Mihail-Calin Ionescu <mihail.ionescu@arm.com>
> 2019-11-14  Sudakshina Das  <sudi.das@arm.com>
>
>         * config/arm/arm.md (ashldi3): Generate thumb2_lsll for both reg
>         and valid immediate.
>         (ashrdi3): Generate thumb2_asrl for both reg and valid immediate.
>         (lshrdi3): Generate thumb2_lsrl for valid immediates.
>         * config/arm/constraints.md (Pg): New.
>         * config/arm/predicates.md (long_shift_imm): New.
>         (arm_reg_or_long_shift_imm): Likewise.
>         * config/arm/thumb2.md (thumb2_asrl): New immediate alternative.
>         (thumb2_lsll): Likewise.
>         (thumb2_lsrl): New.
>
> *** gcc/testsuite/ChangeLog ***
>
> 2019-11-14  Mihail-Calin Ionescu <mihail.ionescu@arm.com>
> 2019-11-14  Sudakshina Das  <sudi.das@arm.com>
>
>         * gcc.target/arm/armv8_1m-shift-imm_1.c: New test.
>
> Testsuite shows no regression when run for arm-none-eabi targets.
>
> Is this ok for trunk?
>

This is ok once the prerequisites are in.

Thanks,

Kyrill


> Thanks
> Mihail
>
>
> ###############     Attachment also inlined for ease of reply    
> ###############
>
>
> diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
> index 
> b735f858a6a5c94d02a6765c1b349cdcb5e77ee3..82f4a5573d43925fb7638b9078a06699df38f88c 
> 100644
> --- a/gcc/config/arm/arm.md
> +++ b/gcc/config/arm/arm.md
> @@ -3509,8 +3509,8 @@
>          operands[2] = force_reg (SImode, operands[2]);
>
>        /* Armv8.1-M Mainline double shifts are not expanded.  */
> -      if (REG_P (operands[2]))
> -       {
> +      if (arm_reg_or_long_shift_imm (operands[2], GET_MODE 
> (operands[2])))
> +        {
>            if (!reg_overlap_mentioned_p(operands[0], operands[1]))
>              emit_insn (gen_movdi (operands[0], operands[1]));
>
> @@ -3547,7 +3547,8 @@
>    "TARGET_32BIT"
>    "
>    /* Armv8.1-M Mainline double shifts are not expanded.  */
> -  if (TARGET_HAVE_MVE && REG_P (operands[2]))
> +  if (TARGET_HAVE_MVE
> +      && arm_reg_or_long_shift_imm (operands[2], GET_MODE (operands[2])))
>      {
>        if (!reg_overlap_mentioned_p(operands[0], operands[1]))
>          emit_insn (gen_movdi (operands[0], operands[1]));
> @@ -3580,6 +3581,17 @@
>                       (match_operand:SI 2 "reg_or_int_operand")))]
>    "TARGET_32BIT"
>    "
> +  /* Armv8.1-M Mainline double shifts are not expanded.  */
> +  if (TARGET_HAVE_MVE
> +    && long_shift_imm (operands[2], GET_MODE (operands[2])))
> +    {
> +      if (!reg_overlap_mentioned_p(operands[0], operands[1]))
> +        emit_insn (gen_movdi (operands[0], operands[1]));
> +
> +      emit_insn (gen_thumb2_lsrl (operands[0], operands[2]));
> +      DONE;
> +    }
> +
>    arm_emit_coreregs_64bit_shift (LSHIFTRT, operands[0], operands[1],
>                                   operands[2], gen_reg_rtx (SImode),
>                                   gen_reg_rtx (SImode));
> diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md
> index 
> b76de81b85c8ce7a2ca484a750b908b7ca64600a..d807818c8499a6a65837f1ed0487e45947f68199 
> 100644
> --- a/gcc/config/arm/constraints.md
> +++ b/gcc/config/arm/constraints.md
> @@ -35,7 +35,7 @@
>  ;;                       Dt, Dp, Dz, Tu
>  ;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe
>  ;; in Thumb-2 state: Ha, Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py, Pz
> -;; in all states: Pf
> +;; in all states: Pf, Pg
>
>  ;; The following memory constraints have been used:
>  ;; in ARM/Thumb-2 state: Uh, Ut, Uv, Uy, Un, Um, Us
> @@ -187,6 +187,11 @@
>                      && !is_mm_consume (memmodel_from_int (ival))
>                      && !is_mm_release (memmodel_from_int (ival))")))
>
> +(define_constraint "Pg"
> +  "@internal In Thumb-2 state a constant in range 1 to 32"
> +  (and (match_code "const_int")
> +       (match_test "TARGET_THUMB2 && ival >= 1 && ival <= 32")))
> +
>  (define_constraint "Ps"
>    "@internal In Thumb-2 state a constant in the range -255 to +255"
>    (and (match_code "const_int")
> diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md
> index 
> 69c10c06ff405e19efa172217a08a512c66cb902..ef5b0303d4424981347287865efb3cca85e56f36 
> 100644
> --- a/gcc/config/arm/predicates.md
> +++ b/gcc/config/arm/predicates.md
> @@ -322,6 +322,15 @@
>                                && (UINTVAL (XEXP (op, 1)) < 32)")))
>         (match_test "mode == GET_MODE (op)")))
>
> +;; True for Armv8.1-M Mainline long shift instructions.
> +(define_predicate "long_shift_imm"
> +  (match_test "satisfies_constraint_Pg (op)"))
> +
> +(define_predicate "arm_reg_or_long_shift_imm"
> +  (ior (match_test "TARGET_THUMB2
> +                   && arm_general_register_operand (op, GET_MODE (op))")
> +       (match_test "satisfies_constraint_Pg (op)")))
> +
>  ;; True for MULT, to identify which variant of shift_operator is in use.
>  (define_special_predicate "mult_operator"
>    (match_code "mult"))
> diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md
> index 
> 3a716ea954ac55b2081121248b930b7f11520ffa..af486d07f428030257855381ff72c32a885b506f 
> 100644
> --- a/gcc/config/arm/thumb2.md
> +++ b/gcc/config/arm/thumb2.md
> @@ -1649,7 +1649,7 @@
>  (define_insn "thumb2_asrl"
>    [(set (match_operand:DI 0 "arm_general_register_operand" "+r")
>          (ashiftrt:DI (match_dup 0)
> -                    (match_operand:SI 1 
> "arm_general_register_operand" "r")))]
> +                    (match_operand:SI 1 "arm_reg_or_long_shift_imm" 
> "rPg")))]
>    "TARGET_HAVE_MVE"
>    "asrl%?\\t%Q0, %R0, %1"
>    [(set_attr "predicable" "yes")])
> @@ -1657,7 +1657,15 @@
>  (define_insn "thumb2_lsll"
>    [(set (match_operand:DI 0 "arm_general_register_operand" "+r")
>          (ashift:DI (match_dup 0)
> -                  (match_operand:SI 1 "arm_general_register_operand" 
> "r")))]
> +                  (match_operand:SI 1 "arm_reg_or_long_shift_imm" 
> "rPg")))]
>    "TARGET_HAVE_MVE"
>    "lsll%?\\t%Q0, %R0, %1"
>    [(set_attr "predicable" "yes")])
> +
> +(define_insn "thumb2_lsrl"
> +  [(set (match_operand:DI 0 "arm_general_register_operand" "+r")
> +       (lshiftrt:DI (match_dup 0)
> +                    (match_operand:SI 1 "long_shift_imm" "Pg")))]
> +  "TARGET_HAVE_MVE"
> +  "lsrl%?\\t%Q0, %R0, %1"
> +  [(set_attr "predicable" "yes")])
> diff --git a/gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c 
> b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c
> new file mode 100644
> index 
> 0000000000000000000000000000000000000000..5ffa3769e6ba42466242d3038857734e87b2f1fc
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c
> @@ -0,0 +1,27 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=armv8.1-m.main+mve -mfloat-abi=softfp" } */
> +
> +long long longval1;
> +long long unsigned longval2;
> +
> +long long int
> +asrl_imm ()
> +{
> + return (longval1 >> 14);
> +}
> +
> +long long unsigned int
> +lsrl_imm ()
> +{
> + return (longval2 >> 14);
> +}
> +
> +long long int
> +lsll_imm (long long int longval3)
> +{
> +  return (longval3 << 14);
> +}
> +
> +/* { dg-final { scan-assembler "asrl\\tr\[0-9\], r\[0-9\], #14" } } */
> +/* { dg-final { scan-assembler "lsrl\\tr\[0-9\], r\[0-9\], #14" } } */
> +/* { dg-final { scan-assembler "lsll\\tr\[0-9\], r\[0-9\], #14" } } */
>

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