[Patch] [Aarch64] PR rtl-optimization/87763 - this patch fixes gcc.target/aarch64/lsl_asr_sbfiz.c
Fri Apr 26 23:59:00 GMT 2019
On Fri, Apr 26, 2019 at 03:54:49PM -0600, Jeff Law wrote:
> > It makes most sense if the mode for extv<mode> is the same both in and out
> > (it has only one mode in the pattern name, to start with), and for
> > sign_extract to be similar. The docs aren't quite clear, but defining it
> > to have multiple modes doesn't really solve anything afaics, subregs work
> > just fine here?
> You'd have to scatter them in the MD file. That's generally frowned upon.
Why would you need that? You just say match_operand:M "register_operand"
and that will match a subreg:M (reg:N) just fine?
And on the outside... Do you have insns that act on DImode regs but only
output to a SImode one?!
> My argument is that we have very clear semantics here. We're taking a
> field from an object in a mode. We zero or sign extract it to the mode
> of the destination. Two modes actually make reasonable sense here.
> Think of it like zero_extend or sign_extend, but for a bitfield.
The pattern with the standard name extv<mode> can only have one mode
obviously... Do you want to define a new standard one (and handle it
everywhere you need to handle it)? Or just have the aarch64 port define
its own non-standard pattern? Or make extv<mode> have semantics that
are different per target, like extv?
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