[PATCH 04/14] S/390: arch13: Add support for new select instruction
Andreas Krebbel
krebbel@linux.ibm.com
Tue Apr 2 11:23:00 GMT 2019
Compared to the load on condition instructions we already have the new
select instruction allows to have a THEN and and ELSE source operand -
but only for register to register loads.
gcc/ChangeLog:
2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com>
* config/s390/s390.c (s390_rtx_costs): Do not add extra costs for
if-then-else constructs if we can use the select instruction.
* config/s390/s390.md ("*mov<mode>cc"): Add the new instructions.
gcc/testsuite/ChangeLog:
2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com>
* gcc.target/s390/arch13/sel-1.c: New test.
---
gcc/config/s390/s390.c | 3 ++-
gcc/config/s390/s390.md | 17 +++++++++--------
gcc/testsuite/gcc.target/s390/arch13/sel-1.c | 21 +++++++++++++++++++++
3 files changed, 32 insertions(+), 9 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/s390/arch13/sel-1.c
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index 7cf1d67..bceaca3 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -3529,7 +3529,8 @@ s390_rtx_costs (rtx x, machine_mode mode, int outer_code,
/* It is a real IF-THEN-ELSE. An additional move will be
needed to implement that. */
- if (reload_completed
+ if (!TARGET_ARCH13
+ && reload_completed
&& !rtx_equal_p (dst, then)
&& !rtx_equal_p (dst, els))
*total += COSTS_N_INSNS (1) / 2;
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 018020c..514bd24 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -6701,27 +6701,28 @@
-; locr, loc, stoc, locgr, locg, stocg, lochi, locghi
+; locr, loc, stoc, locgr, locg, stocg, lochi, locghi, selr, selgr
(define_insn "*mov<mode>cc"
- [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,S,S")
+ [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,S,S")
(if_then_else:GPR
(match_operator 1 "s390_comparison"
- [(match_operand 2 "cc_reg_operand" " c,c,c,c,c,c,c,c")
- (match_operand 5 "const_int_operand" "")])
- (match_operand:GPR 3 "loc_operand" " d,0,S,0,K,0,d,0")
- (match_operand:GPR 4 "loc_operand" " 0,d,0,S,0,K,0,d")))]
+ [(match_operand 2 "cc_reg_operand" " c,c,c,c,c,c,c,c,c")
+ (match_operand 5 "const_int_operand" "")])
+ (match_operand:GPR 3 "loc_operand" " d,0,d,S,0,K,0,d,0")
+ (match_operand:GPR 4 "loc_operand" " 0,d,d,0,S,0,K,0,d")))]
"TARGET_Z196"
"@
loc<g>r%C1\t%0,%3
loc<g>r%D1\t%0,%4
+ sel<g>r%C1\t%0,%3,%4
loc<g>%C1\t%0,%3
loc<g>%D1\t%0,%4
loc<g>hi%C1\t%0,%h3
loc<g>hi%D1\t%0,%h4
stoc<g>%C1\t%3,%0
stoc<g>%D1\t%4,%0"
- [(set_attr "op_type" "RRF,RRF,RSY,RSY,RIE,RIE,RSY,RSY")
- (set_attr "cpu_facility" "*,*,*,*,z13,z13,*,*")])
+ [(set_attr "op_type" "RRF,RRF,RRF,RSY,RSY,RIE,RIE,RSY,RSY")
+ (set_attr "cpu_facility" "*,*,arch13,*,*,z13,z13,*,*")])
;;
;;- Multiply instructions.
diff --git a/gcc/testsuite/gcc.target/s390/arch13/sel-1.c b/gcc/testsuite/gcc.target/s390/arch13/sel-1.c
new file mode 100644
index 0000000..301a133
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/arch13/sel-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+
+int
+sel32 (int a, int then, int els)
+{
+ return a > 42 ? then : els;
+}
+
+/* FIXME: This currently fails since ifcvt considers that combination
+ too expensive. THe reason is that additional load instructions
+ emitted by ifcvt are part of the costs although these should get
+ removed later. */
+/* { dg-final { scan-assembler-times "\tselrh\t" 1 } } */
+
+long long
+sel64 (int a, long long then, long long els)
+{
+ return a > 42 ? then : els;
+}
+
+/* { dg-final { scan-assembler-times "\tselgrh\t" 1 } } */
--
2.7.4
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