[PATCH][GCC][AARCH64] Add even-pair register classes

[Wilco Dijkstra]

Matthew wrote:

> The canonical way to require even-odd pairs of registers to implement a TImode
> pseudo register as mentioned in the documentation is to limit *all* TImode
> registers to being even-odd by using the TARGET_HARD_REGNO_MODE_OK hook.

And that is the best approach for cases like this. Adding new register classes is rarely
a good idea since they complicate matters and slow down the register allocator. We've 
had several cases where a new register class caused unexpected code quality issues.
How do we know that won't happen this time?

> We don't want to use this method as it would apply to all register pairs.

Why not? From our Arm/Thumb-2 experiments on DImode splitting and allocation we 
know even/odd pairs give a better allocation, and there are fewer cases where the
allocation completely fails under high register pressure.

> (It is noteworthy that the current cost model in ira prefers to put values that
> span two registers in an even-odd pair anyway, so the use of
> TARGET_HARD_REGNO_MODE_OK would likely not cause much change in low register
> pressure situations)

Exactly. TImode is not used that much (unlike DImode on Arm/Thumb-2), so it would
be hard to find any difference.

So I would strongly suggest to keep things simple and just use even/odd pairs. Adding a
new register class is generally not worth it unless you can show it will significantly improve
code quality.

Wilco