[PATCH, i386]: Do not use "u" constraint and remove FP_TOP_SSE_REGS and FP_SECOND_SSE_REGS register classes

Uros Bizjak ubizjak@gmail.com
Wed Sep 26 15:26:00 GMT 2018 

Hello!

Stack registers are fixed up by regstack pass, so there is no point to
specify "upper" FP register in the instruction patterns. This change
allows register allocator a bit more freedom, which results in a few
fxch instructions less.

The patch also removes FP_TOP_SSE_REGS and FP_SECOND_SSE_REGS mixed
classes. We don't have any insn patterns that would allow the mix of
"t"/"u" and SSE regs, so the class is neverused.

Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.

Committed to mainline SVN.

Uros.
-------------- next part --------------
Index: config/i386/i386.c
===================================================================
--- config/i386/i386.c	(revision 264643)
+++ config/i386/i386.c	(working copy)
@@ -39043,10 +39043,6 @@ ix86_preferred_reload_class (rtx x, reg_class_t re
 	  /* Limit class to FP regs.  */
 	  if (FLOAT_CLASS_P (regclass))
 	    return FLOAT_REGS;
-	  else if (regclass == FP_TOP_SSE_REGS)
-	    return FP_TOP_REG;
-	  else if (regclass == FP_SECOND_SSE_REGS)
-	    return FP_SECOND_REG;
 	}
 
       return NO_REGS;
@@ -39092,14 +39088,7 @@ ix86_preferred_output_reload_class (rtx x, reg_cla
     return MAYBE_SSE_CLASS_P (regclass) ? ALL_SSE_REGS : NO_REGS;
 
   if (IS_STACK_MODE (mode))
-    {
-      if (regclass == FP_TOP_SSE_REGS)
-	return FP_TOP_REG;
-      else if (regclass == FP_SECOND_SSE_REGS)
-	return FP_SECOND_REG;
-      else
-	return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS;
-    }
+    return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS;
 
   return regclass;
 }
Index: config/i386/i386.h
===================================================================
--- config/i386/i386.h	(revision 264645)
+++ config/i386/i386.h	(working copy)
@@ -1337,8 +1337,6 @@ enum reg_class
   SSE_REGS,
   ALL_SSE_REGS,
   MMX_REGS,
-  FP_TOP_SSE_REGS,
-  FP_SECOND_SSE_REGS,
   FLOAT_SSE_REGS,
   FLOAT_INT_REGS,
   INT_SSE_REGS,
@@ -1398,8 +1396,6 @@ enum reg_class
    "SSE_REGS",				\
    "ALL_SSE_REGS",			\
    "MMX_REGS",				\
-   "FP_TOP_SSE_REGS",			\
-   "FP_SECOND_SSE_REGS",		\
    "FLOAT_SSE_REGS",			\
    "FLOAT_INT_REGS",			\
    "INT_SSE_REGS",			\
@@ -1438,8 +1434,6 @@ enum reg_class
 { 0x1fe00000,   0x1fe000,    0x0 },	/* SSE_REGS */			\
 { 0x1fe00000, 0xffffe000,   0x1f },	/* ALL_SSE_REGS */		\
 { 0xe0000000,       0x1f,    0x0 },	/* MMX_REGS */			\
-{ 0x1fe00100, 0xffffe000,   0x1f },	/* FP_TOP_SSE_REG */		\
-{ 0x1fe00200, 0xffffe000,   0x1f },	/* FP_SECOND_SSE_REG */		\
 { 0x1fe0ff00, 0xffffe000,   0x1f },	/* FLOAT_SSE_REGS */		\
 {   0x11ffff,     0x1fe0,    0x0 },	/* FLOAT_INT_REGS */		\
 { 0x1ff100ff, 0xffffffe0,   0x1f },	/* INT_SSE_REGS */		\
Index: config/i386/i386.md
===================================================================
--- config/i386/i386.md	(revision 264643)
+++ config/i386/i386.md	(working copy)
@@ -4973,7 +4973,7 @@
 (define_insn "fix_trunc<mode>_i387_fisttp"
   [(set (match_operand:SWI248x 0 "nonimmediate_operand" "=m")
 	(fix:SWI248x (match_operand 1 "register_operand" "f")))
-   (clobber (match_scratch:XF 2 "=&1f"))]
+   (clobber (match_scratch:XF 2 "=&f"))]
   "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
    && TARGET_FISTTP
    && !((SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
@@ -5019,7 +5019,7 @@
 	(fix:DI (match_operand 1 "register_operand" "f")))
    (use (match_operand:HI 2 "memory_operand" "m"))
    (use (match_operand:HI 3 "memory_operand" "m"))
-   (clobber (match_scratch:XF 4 "=&1f"))]
+   (clobber (match_scratch:XF 4 "=&f"))]
   "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
    && !TARGET_FISTTP
    && !(TARGET_64BIT && SSE_FLOAT_MODE_P (GET_MODE (operands[1])))"
@@ -15178,7 +15178,7 @@
 	(unspec:XF [(match_operand:XF 2 "register_operand" "0")
 		    (match_operand:XF 3 "register_operand" "1")]
 		   UNSPEC_FPREM_F))
-   (set (match_operand:XF 1 "register_operand" "=u")
+   (set (match_operand:XF 1 "register_operand" "=f")
 	(unspec:XF [(match_dup 2) (match_dup 3)]
 		   UNSPEC_FPREM_U))
    (set (reg:CCFP FPSR_REG)
@@ -15253,7 +15253,7 @@
 	(unspec:XF [(match_operand:XF 2 "register_operand" "0")
 		    (match_operand:XF 3 "register_operand" "1")]
 		   UNSPEC_FPREM1_F))
-   (set (match_operand:XF 1 "register_operand" "=u")
+   (set (match_operand:XF 1 "register_operand" "=f")
 	(unspec:XF [(match_dup 2) (match_dup 3)]
 		   UNSPEC_FPREM1_U))
    (set (reg:CCFP FPSR_REG)
@@ -15365,7 +15365,7 @@
   [(set (match_operand:XF 0 "register_operand" "=f")
 	(unspec:XF [(match_operand:XF 2 "register_operand" "0")]
 		   UNSPEC_SINCOS_COS))
-   (set (match_operand:XF 1 "register_operand" "=u")
+   (set (match_operand:XF 1 "register_operand" "=f")
         (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
   "TARGET_USE_FANCY_MATH_387
    && flag_unsafe_math_optimizations"
@@ -15397,7 +15397,7 @@
 (define_insn "fptanxf4_i387"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(match_operand:SF 3 "const1_operand"))
-   (set (match_operand:XF 1 "register_operand" "=u")
+   (set (match_operand:XF 1 "register_operand" "=f")
         (unspec:XF [(match_operand:XF 2 "register_operand" "0")]
 		   UNSPEC_TAN))]
   "TARGET_USE_FANCY_MATH_387
@@ -15439,7 +15439,7 @@
 (define_insn "atan2xf3"
   [(set (match_operand:XF 0 "register_operand" "=f")
         (unspec:XF [(match_operand:XF 1 "register_operand" "0")
-	            (match_operand:XF 2 "register_operand" "u")]
+	            (match_operand:XF 2 "register_operand" "f")]
 	           UNSPEC_FPATAN))
    (clobber (match_scratch:XF 3 "=2"))]
   "TARGET_USE_FANCY_MATH_387
@@ -15576,7 +15576,7 @@
 (define_insn "fyl2xxf3_i387"
   [(set (match_operand:XF 0 "register_operand" "=f")
         (unspec:XF [(match_operand:XF 1 "register_operand" "0")
-		    (match_operand:XF 2 "register_operand" "u")]
+		    (match_operand:XF 2 "register_operand" "f")]
 	           UNSPEC_FYL2X))
    (clobber (match_scratch:XF 3 "=2"))]
   "TARGET_USE_FANCY_MATH_387
@@ -15673,7 +15673,7 @@
 (define_insn "fyl2xp1xf3_i387"
   [(set (match_operand:XF 0 "register_operand" "=f")
         (unspec:XF [(match_operand:XF 1 "register_operand" "0")
-		    (match_operand:XF 2 "register_operand" "u")]
+		    (match_operand:XF 2 "register_operand" "f")]
 	           UNSPEC_FYL2XP1))
    (clobber (match_scratch:XF 3 "=2"))]
   "TARGET_USE_FANCY_MATH_387
@@ -15714,7 +15714,7 @@
   [(set (match_operand:XF 0 "register_operand" "=f")
 	(unspec:XF [(match_operand:XF 2 "register_operand" "0")]
 		   UNSPEC_XTRACT_FRACT))
-   (set (match_operand:XF 1 "register_operand" "=u")
+   (set (match_operand:XF 1 "register_operand" "=f")
         (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))]
   "TARGET_USE_FANCY_MATH_387
    && flag_unsafe_math_optimizations"
@@ -15808,7 +15808,7 @@
 	(unspec:XF [(match_operand:XF 2 "register_operand" "0")
 		    (match_operand:XF 3 "register_operand" "1")]
 		   UNSPEC_FSCALE_FRACT))
-   (set (match_operand:XF 1 "register_operand" "=u")
+   (set (match_operand:XF 1 "register_operand" "=f")
 	(unspec:XF [(match_dup 2) (match_dup 3)]
 		   UNSPEC_FSCALE_EXP))]
   "TARGET_USE_FANCY_MATH_387
@@ -16193,7 +16193,7 @@
   [(set (match_operand:DI 0 "nonimmediate_operand" "=m")
 	(unspec:DI [(match_operand:XF 1 "register_operand" "f")]
 		   UNSPEC_FIST))
-   (clobber (match_scratch:XF 2 "=&1f"))]
+   (clobber (match_scratch:XF 2 "=&f"))]
   "TARGET_USE_FANCY_MATH_387"
   "* return output_fix_trunc (insn, operands, false);"
   [(set_attr "type" "fpspc")
@@ -16404,7 +16404,7 @@
 		   FIST_ROUNDING))
    (use (match_operand:HI 2 "memory_operand" "m"))
    (use (match_operand:HI 3 "memory_operand" "m"))
-   (clobber (match_scratch:XF 4 "=&1f"))]
+   (clobber (match_scratch:XF 4 "=&f"))]
   "TARGET_USE_FANCY_MATH_387
    && flag_unsafe_math_optimizations"
   "* return output_fix_trunc (insn, operands, false);"

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