[PATCH][GCC][AARCH64] enable STLUR use: Use STLUR in atomic_store

[Richard Earnshaw (lists)]

On 18/09/18 16:36, Matthew Malcomson wrote:
> 
>>> diff --git a/gcc/config/aarch64/atomics.md
>>> b/gcc/config/aarch64/atomics.md
>>> index
>>> 36c06756a1f94cadae097b3aad654fbeba1cf2f3..73078e412d01a43c05195f01488b95a2bc7a20ec
>>> 100644
>>> --- a/gcc/config/aarch64/atomics.md
>>> +++ b/gcc/config/aarch64/atomics.md
>>> @@ -481,9 +481,9 @@
>>> Â  )
>>> Â  Â  (define_insn "atomic_store<mode>"
>>> -Â  [(set (match_operand:ALLI 0 "aarch64_sync_memory_operand" "=Q")
>>> +Â  [(set (match_operand:ALLI 0 "aarch64_9bit_offset_memory_operand"
>>> "=Q,Ust")
>> This is less than ideal because on earlier architectures the predicate
>> will allow the offset variants but register allocation will then have to
>> undo that to match the first alternative.
>>
>> I think what we should do is define a wrapped variant of
>> aarch64_9bit_offset_memory_operand which uses that function but only
>> allows the offset when RCPC8_4 is enabled.
>>
>> Something like
>>
>> aarch64_rcpc_memory_operand (...)
>> {
>> Â Â  if (TARGET_RCPC8_4)
>> Â Â Â Â  return aarch64_9bit_offset_memory_operand (...);
>> Â Â  return aarch64_sync_memory_operand (...);
>> }
>>
>> OK with that change.
>>
>> R.
>>
>>
> 
> Is defining that in the predicates.md file like the below OK?
> Â (just to keep the new predicates together and so it can be found in
> predicates.md)
> 
> 
> (define_predicate "aarch64_rcpc_memory_operand"
> Â  (if_then_else (match_test "AARCH64_ISA_RCPC8_4")
> Â Â Â  (match_operand 0 "aarch64_9bit_offset_memory_operand")
> Â Â Â  (match_operand 0 "aarch64_sync_memory_operand")))
> 
> 
> 

Sure.

R.